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VT82C691 preliminary revision 1.0 july 16, 1998 - i- revision history 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw r evision h istory document release date revision initials 0.1 11/11/97 initial internal release based on apollo mvp3 data sheet revision 0.5 replaced cpu interface pin descriptions from apollo p6 data sheet dh 0.2 12/15/97 incorporated changes based on internal document review added preliminary pinouts updated mechanical specification to reflect 492-ball bga dh 0.3 12/18/97 updated pinouts to proposed pinout dh 0.4 1/30/98 updated pinouts to final pinout fixed cpu/dram frequency strapping options (moved to mecc0 and 2) dh 0.5 2/13/98 updated feature bullets fixed gtlref pin number in pin descriptions moved strapping options from ha to mecc (pclk description, rx68-69) updated register and bit definitions: added rx2c subsystem vendor id and rx2e subsystem id added clarifying note on rx50[7] redefined rx51 all bits added rx52[7] (strap mecc4) gtl pullup enable added rx6b[3-1] suspend refresh rate changed rx6c[7] to reserved / do not program added rx6d[7] mab output disable removed rx70[5] (no function) and added new bits rx70[3,0], rx73[4] swapped 0/1 bit definition for rx78[5] added rxf0-f7 bios scratch registers dh 0.6 2/17/98 removed internal cpu frequency comment in feature bullets added bios scratch registers to register summary tables fixed typos in rx51[5] and rx70[0] dh 1.0 7/16/98 changed 586b to 596 in apollo pro chipset removed ddr, virtual channel, and esdram feature bullets fixed feature bullet / overview errors regarding writeback & edo timing changed device 0 rx78[4] to reserved, do not program updated agp spec support from 1.0 to 2.0 dh
VT82C691 preliminary revision 1.0 july 16, 1998 - ii- table of contents 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw t able of c ontents revision history............................................................................................................... .........................................................i table of contents.............................................................................................................. .................................................... ii list of figures................................................................................................................ ..........................................................iii list of tables ................................................................................................................. ..........................................................iv apollo pro ..................................................................................................................... .............................................................. 1 overview ....................................................................................................................... ................................................................ 4 pinouts C VT82C691 apollo pro.................................................................................................. ......................................... 6 pin descriptions ............................................................................................................... ......................................................... 9 registers ...................................................................................................................... ............................................................... 17 r egister o verview ............................................................................................................................... .................................. 17 m iscellaneous i/o............................................................................................................................ ....................................... 20 c onfiguration s pace i/o ............................................................................................................................ ........................... 20 r egister d escriptions ............................................................................................................................... ............................. 21 device 0 header registers - host bridge........................................................................................ .................................... 21 device 0 configuration registers - host bridge ................................................................................. ............................... 23 host cpu control ............................................................................................................... .................................................................. 23 dram control ................................................................................................................... .................................................................. 24 pci bus #1 control............................................................................................................. .................................................................. 30 gart / graphics aperture control ............................................................................................... ....................................................... 33 agp control .................................................................................................................... ..................................................................... 35 device 1 header registers - pci-to-pci bridge .................................................................................. .............................. 37 device 1 configuration registers - pci-to-pci bridge........................................................................... .......................... 40 pci bus #2 control............................................................................................................. .................................................................. 40 electrical specifications...................................................................................................... ......................................... 41 a bsolute m aximum r atings ............................................................................................................................... .................. 41 dc c haracteristics ............................................................................................................................... ................................. 41 ac t iming s pecifications ............................................................................................................................... ....................... 41 mechanical specifications ...................................................................................................... ....................................... 47
VT82C691 preliminary revision 1.0 july 16, 1998 - iii- list of figures 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw l ist of f igures figure 1. apollo pro system block diagram using the vt82c596 mobile south bridge.............. 4 figure 2. VT82C691 ball diagram (top view).................................................................................... .......................... 6 figure 3. VT82C691 pin list (numerical order) ........................................................................................................ 7 figure 4. VT82C691 pin list (alphabetical order).................................................................................................. 8 figure 5. graphics aperture address translation ............................................................................... .......... 33 figure 8. mechanical specifications - 492-pin ball grid array package ........................................... 47
VT82C691 preliminary revision 1.0 july 16, 1998 - iv- list of tables 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw l ist of t ables table 1. VT82C691 pin descriptions ............................................................................................ ..................................... 9 table 2. VT82C691 registers ................................................................................................... ........................................... 17 table 3. system memory map.................................................................................................... ...................................... 24 table 4. memory address mapping table ......................................................................................... ...................... 24 table 5. vga/mda memory/io redirection........................................................................................ ...................... 40 table 6. ac timing min / max conditions....................................................................................... ........................... 41 table 7. ac characteristics - cpu cycle timing ................................................................................ ................ 42 table 8. ac characteristics - dram interface timing........................................................................... ........ 43 table 9. ac characteristics - data timing ..................................................................................... ....................... 43 table 10. ac characteristics - pci cycle timing.............................................................................. ................. 44 table 11. ac characteristics C pci-66 cycle timing............................................................................ .............. 45 table 12. ac characteristics - agp (1x) cycle timing.......................................................................... ............ 46 table 13. ac characteristics - agp (2x) cycle timing.......................................................................... ............ 46
VT82C691 preliminary revision 1.0 july 16, 1998 - 1- features 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw via VT82C691 a pollo p ro 66 / 100 mhz single-chip socket-8 / slot-1 north bridge for desktop and mobile pc systems with agp and pci plus advanced ecc memory controller supporting sdram, edo, and fpg agp / pci / isa mobile and deep green pc ready - supports 3.3v and sub-3.3v interface to cpu - supports separately powered 3.3v (5v tolerant) interface to system memory, agp, and pci bus - pc-98 compatible using via south bridge chips vt82c586b (208-pin pqfp) or vt82c596 (324-contact bga) with acpi power management for cost-efficient desktop applications - modular power management and clock control for mobile system applications - combine with via vt82c596 (intel piix4 pin compatible 324-pin bga) mobile south south bridge chip for state-of-the-art mobile applications high integration - single chip implementation for 64-bit socket-8 / slot-1-cpu, 64-bit system memory, 32-bit pci and 32-bit agp interfaces - apollo pro chipset: VT82C691 system controller and vt82c596 pci to isa bridge - chipset includes ultradma-33 eide, usb, and keyboard / ps2-mouse interfaces plus rtc / cmos on chip high performance cpu interface - supports socket-8 (intel pentium pro tm ) and slot-1 (intel pentium ii tm ) processors - 66 / 100 mhz cpu external bus speed - built-in deskew dll (delay lock loop) circuitry for optimal skew control within and between clocking regions - five outstanding transactions (four in-order queue (ioq) plus one input latch) - supports wc (write combining) cycles - dynamic deferred transaction support - sleep mode support - system management interrupt, memory remap and stpclk mechanism
VT82C691 preliminary revision 1.0 july 16, 1998 - 2- features 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw full featured accelerated graphics port (agp) controller - synchronous and pseudo-synchronous with the host cpu bus with optimal skew control pci agp cpu mode 33 mhz 66 mhz 100 mhz 3x synchronous 33 mhz 66 mhz 66 mhz 2x synchronous - agp v2.0 compliant (1x and 2x transfer modes) - supports sideband addressing (sba) mode (non-multiplexed address / data) - supports 133mhz 2x mode for ad and sba signalling - pipelined split-transaction long-burst transfers up to 533 mb/sec - eight level read request queue - four level posted-write request queue - thirty-two level (quadwords) read data fifo (128 bytes) - sixteen level (quadwords) write data fifo (64 bytes) - intelligent request reordering for maximum agp bus utilization - supports flush/fence commands - graphics address relocation table (gart) - one level tlb structure - sixteen entry fully associative page table - lru replacement scheme - independent gart lookup control for host / agp / pci master accesses - windows 95 osr-2 vxd and integrated windows 98 / nt5 miniport driver support concurrent pci bus controller - pci buses are synchronous / pseudo-synchronous to host cpu bus - 33 mhz operation on the primary pci bus - 66 mhz pci operation on the agp bus - pci-to-pci bridge configuration on the 66mhz pci bus - supports up to five pci masters - peer concurrency - concurrent multiple pci master transactions; i.e., allow pci masters from both pci buses active at the same time - zero wait state pci master and slave burst transfer rate - pci to system memory data streaming up to 132mbyte/sec - pci master snoop ahead and snoop filtering - five levels (double-words) of cpu to pci posted write buffers - byte merging in the write buffers to reduce the number of pci cycles and to create further pci bursting possibilities - enhanced pci command optimization (mrl, mrm, mwi, etc.) - forty-eight levels (double-words) of post write buffers from pci masters to dram - sixteen levels (double-words) of prefetch buffers from dram for access by pci masters - delay transaction from pci master accessing dram - read caching for pci master reading dram - transaction timer for fair arbitration between pci masters (granularity of two pci clocks) - symmetric arbitration between host/pci bus for optimized system performance - complete steerable pci interrupts - pci-2.1 compliant, 32 bit 3.3v pci interface with 5v tolerant inputs
VT82C691 preliminary revision 1.0 july 16, 1998 - 3- features 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw advanced high-performance dram controller - dram interface synchronous with host cpu (66/100 mhz) or agp (66mhz) for most flexible configuration - concurrent cpu, agp, and pci access - fp, edo, and sdram (standard speed and pc100) - different dram types may be used in mixed combinations - different dram timing for each bank - dynamic clock enable (cke) control for sdram power reduction in mobile and desktop systems - mixed 1m / 2m / 4m / 8m / 16mxn drams - 8 banks up to 1gb drams - flexible row and column addresses - 64-bit data width only - 3.3v dram interface with 5v-tolerant inputs - programmable i/o drive capability for ma, command, and md signals - dual copies of ma signals for improved drive - optional bank-by-bank ecc (single-bit error correction and multi-bit error detection) or ec (error checking only) for dram integrity - two-bank interleaving for 16mbit sdram support - two-bank and four bank interleaving for 64mbit sdram support - supports maximum 16-bank interleave (i.e., 16 pages open simultaneously); banks are allocated based on lru - independent sdram control for each bank - seamless dram command scheduling for maximum dram bus utilization (e.g., precharge other banks while accessing the current bank) - four cache lines (16 quadwords) of cpu to dram write buffers - four quadwords of cpu to dram read prefetch buffers - read around write capability for non-stalled cpu read - speculative dram read before snoop result - burst read and write operation - x-2-2-2-2-2-2-2 back-to-back accesses for edo dram - x-1-1-1-2-1-1-1 back-to-back accesses for sdram - bios shadow at 16kb increment - decoupled and burst dram refresh with staggered ras timing - programmable refresh rate and refresh on populated banks only - cas before ras or self refresh mobile system support - independent clock stop controls for cpu / sdram, agp, and pci bus - pci and agp bus clock run and clock generator control - vtt suspend power plane preserves memory data - suspend-to-dram and self-refresh operation - dynamic clock gating for internal functional blocks for power reduction during normal operation - low-leakage i/o pads built-in nand-tree pin scan test capability 3.3v, 0.35um, high speed / low power cmos process 35 x 35 mm, 492 pin bga package
VT82C691 preliminary revision 1.0 july 16, 1998 - 4- overview 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw o verview the apollo pro is a high performance, cost-effective and energy efficient chip set for the implementation of agp / pci / isa desktop and notebook personal computer systems from 66 mhz to 100 mhz based on 64-bit socket-8 (intel pentium pro) and slot-1 (intel pentium-ii) super-scalar processors. pckrun# pclk hclk gclk socket-8 or slot-1 host cpu cke# memory bus smbus isa VT82C691 north bridge 492 bga fpm, edo, or sdram 3d graphics controller agp bus pcistp# power plane & peripheral control bios rom gckrun# pci bus ide usb gpio and acpi events vt82c596 mobile south 324 bga ke y board / mouse cpustp# clock generator mclk hclk gclk pclk smi# / stpclk# / slp# susclk, susst1# smiact# figure 1. apollo pro system block diagram using the vt82c596 mobile south bridge the apollo-pro chip set consists of the VT82C691 system controller (492 pin bga) and the vt82c596 pci to isa bridge (324 pin bga). the system controller provides superior performance between the cpu, dram, agp bus, and pci bus with pipelined, burst, and concurrent operation. four cache lines (16 quadwords) of cpu to dram write buffers are included on chip to speed up write cycle performance. the VT82C691 supports eight banks of drams up to 1gb. the dram controller supports standard fast page mode (fpm) dram, edo-dram, and synchronous dram (sdram) in a flexible mix / match manner. the synchronous dram interface allows zero wait state bursting between the dram and the data buffers at 100 mhz. the eight banks of dram can be composed of an arbitrary mixture of 1m / 2m / 4m / 8m / 16mxn drams. the dram controller also supports optional ecc (single-bit error correction and multi-bit detection) or ec (error checking) capability separately selectable on a bank-by-bank basis. the dram controller can run at either the host cpu bus frequency (66 /100 mhz) or at the agp bus frequency (66 mhz) with built- in deskew dll timing control. coupled with pc100 sdram, the VT82C691 allows implementation of the most flexible, reliable, and high-performance dram interface with data transfers at 66 or 100 mhz. the VT82C691 also supports full agp v2.0 capability for maximum bus utilization including 2x mode transfers, sba (sideband addressing), flush/fence commands, and pipelined grants. an eight level request queue plus a four level post-write request que ue with thirty-two and sixteen quadwords of read and write data fifo's respectively are included for deep pipelined and split agp transactions. a single-level gart tlb with 16 full associative entries and flexible cpu / agp / pci remapping control is also provided for operation under protected mode operating environments. both windows-95 vxd and windows-98 / nt5 miniport drivers are supported for interoperability with major agp-based 3d and dvd-capable multimedia accelerators. the VT82C691 supports two 32-bit 3.3 / 5v system buses (one agp and one pci) that are synchronous / pseudo-synchronous to the cpu bus. the chip also contains a built-in bus-to-bus bridge to allow simultaneous concurrent operations on each bus. fiv e levels (doublewords) of post write buffers are included to allow for concurrent cpu and pci operation. for pci master operatio n, forty-eight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for concurrent pci bus and dram/cache accesses. the chip also supports enhanced pci bus commands such as memory-read-line, memory-read-multiple and memory-write-invalid commands to minimize snoop overhead. in addition, advanced features are supported such as snoop ahead, snoop filtering, l1 write-back forward to pci master, and l1 write-back merged with pci post
VT82C691 preliminary revision 1.0 july 16, 1998 - 5- overview 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw write buffers to minimize pci master read latency and dram utilization. delay transaction and read caching mechanisms are also implemented for further improvement of overall system performance. the 324-pin ball grid array vt82c596 pci to isa bridge supports four levels (doublewords) of line buffers, type f dma transfers and delay transaction to allow efficient pci bus utilization and (pci-2.1 compliant). the vt82c596 also includes an integrated keyboard controller with ps2 mouse support, integrated ds12885 style real time clock with extended 256 byte cmos ram, integrated master mode enhanced ide controller with full scatter and gather capability and extension to ultradma-33 / ata-33 for 33mb/sec transfer rate, integrated usb interface with root hub and two function ports with built-in physical layer transceivers, distributed dma support, and onnow / acpi compliant advanced configuration and power management interface. for sophisticated notebook implementations, the VT82C691 provides independent clock stop control for the cpu / sdram, pci, and agp buses and dynamic cke control for powering down of the sdram. a separate suspend-well plane is implemented for the sdram control signals for suspend-to-dram operation. coupled with the vt82c596 mobile south chip, a complete notebook pc main board can be implemented with no external ttls. the apollo pro chipset is ideal for high performance, high quality, high energy efficient and high integration desktop and note book agp / pci / isa computer systems.
VT82C691 preliminary revision 1.0 july 16, 1998 - 6- pinouts C VT82C691 apollo pro 7hfkqrorjlhv ,qf : h& : h&r rqqhfw qqhfw p inouts C VT82C691 a pollo p ro figure 2. VT82C691 ball diagram (top view) ke y 1234567891011121314151617181920212223242526 a gnd gd29 sba6 sba5 sba3 sba0 init# hd58# hd53# hd63# hd54# hd57# gnd hd47# hd45# hd34# hd33# hd29# hd24# hd23# hd20# hd10# hd6# hd5# hd1# gnd b gd27 gd30 sba7 sba4 sba2 grbf# greq# hd61# hd50# hd56# hd60# hd52# hd51# hd42# hd39# hd37# hd28# hd30# hd22# hd18# hd13# hd12# hd8# hd0# ha30 ha29 c gd28 gd31 gnd sbs# sba1 gpipe# ggnt# vcc3 hd48# hd62# hd55# hd59# hd46# gnd hd36# hd38# hd31# hd25# vcc3 hd16# hd15# hd14# hd4# gnd ha26 ha31 d gd25 gd24 gd26 gvref gd23 gds1# st2 hd49# hd44# hd43# hd32# gtl ref hd35# mclko hd26# mclki hd27# hd19# hd11# hd9# hd3# cpurst# gtl ref ha28 ha22 ha20 e gd18 gd19 gd21 gd22 gnd st0 st1 hd41# hd40# gclk agnd vtt gnd gnd avcc hclk agnd hd21# hd17# hd7# hd2# gnd breq0# ha23 ha25 ha19 f gtrdy# gfrm# gd17 gd16 gbe3# gnd vcc3 vcc3 vcc3 avcc 11 12 13 14 15 16 vtt vcc3 vcc3 vcc3 gnd ha24 ha27 ha15 ha18 ha11 g gd13 gpar gstp# gd20 gbe2# gnd g7 8 9 10 17 18 19 g20 gnd ha17 ha21 ha13 ha12 ha14 h gd10 gd11 vcc3 gserr# girdy# vcc3 h 9 h vcc3 ha16 ha7 vcc3 ha5 ha3 j gd7 gd8 gd9 gd15 gdsel# vcc3 j agp cpu j vcc3 ha10 ha8 ha9 ha4 bnr# k gd6 gd5 gds0# gd14 gbe1# gd12 k pins k10 11 12 13 14 15 16 k17 pins kvtt ha6 hreq1# hreq0# bpri# hreq4# l gd3 gd2 gd4 gd1 gbe0# l l gnd vcc3 gnd gnd vcc3 gnd l l htrdy# drdy# defer# hlock# hreq2# m req3# gnt2# req2# lock# gd0 m m vcc3 gnd gnd gnd gnd vcc3 m m hreq3# rs2# rs0# hitm# hit# n gnt1# req1# gnd gnt3# gnd n n gnd gnd gnd gnd gnd gnd n n gnd ads# dbsy# rs1# gnd p gnd req0# ad31 gnt0# gnd p p gnd gnd gnd gnd gnd gnd p p gnd md0 gnd md2 md34 r ad30 ad29 ad28 req4# gnt4# r r vcc3 gnd gnd gnd gnd vcc3 r r md1 md32 md3 md35 md4 t ad27 ad25 ad24 ad26 pclk t t gnd vcc3 gnd gnd vcc3 gnd t t md6 md33 md36 md5 md37 u cbe3# ad21 ad20 ad23 ad22 5vref u pci u10111213141516u17 dram uvsus md7 md38 md8 md40 md9 v ad19 ad16 cbe2# ad18 ad17 vcc3 v pins pins v vcc3 md11 md39 md41 md10 md42 w frm# irdy# vcc3 trdy# par vcc3 w w vcc3 md13 md43 vcc3 md12 md44 y dsel# stop# serr# ad13 cbe1# gndy78 9 10 171819y20gnd md47 md45 md14 md46 md15 aa ad15 ad14 ad11 ad12 ad8 gnd vcc3 vcc3 vcc3 md22 11 12 13 14 15 16 5vref vcc3 vcc3 vcc3 gnd mecc0 mecc4 mecc5 swec# ras0# ab ad10 ad9 ad7 cbe0# gnd sust# md58 vsus md23 md51 md19 md18 gnd gnd ds3# cas2# cas6# ras5# scasd# maa13 mab0 gnd mecc1 swea# scasa# cas4# ac ad6 ad5 reset# crsti# md30 md27 md26 md55 md21 md54 md50 mvref ds7# ds6# maa2 ds2# cas3# cas7# mab10 mab7 maa11 maa3 ds1# ras1# scasc# ds0# ad ad3 ad0 gnd md63 md60 suclk md56 vcc3 md49 md16 mecc2 mecc3 gnd maa9 mab5 swed# ras4# mab8 vcc3 maa7 maa0 mvref maa4 gnd ds5# ds4# ae ad4 ad1 pgnt# md62 md29 md59 md25 md53 md20 md48 mecc6 mab12 srasd# maa10 maa12 mab9 ras3# ras6# mab3 maa8 maa1 ras2# cas0# maa6 srasc# srasb# af gnd ad2 preq# md31 md61 md28 md57 md24 md52 md17 mecc7 mab13 mab11 gnd maa5 mab4 sweb# ras7# mab6 mab2 srasa# cas5# cas1# scasb# mab1 gnd
VT82C691 preliminary revision 1.0 july 16, 1998 - 7- pinouts C VT82C691 apollo pro 7hfkqrorjlhv ,qf : h& : h&r rqqhfw qqhfw figure 3. VT82C691 pin list (numerical order) pin # pin name pin # pin name pin # pin name pin # pin name pin # pin names pin # pin name a01 p gnd d05 io gd23 h03 p vcc3 p01 p gnd w25 io md12 ac23 o ds1# a02 io gd29 d06 io gds1# h04 io gserr# / pckr# p02 i re q 0# w26 io md44 ac24 o ras1# / cs1# a03 i sba6 d07 o st2 h05 io girdy# p03 io ad31 y01 io devsel# ac25 o scasc# a04 i sba5 d08 io hd49# h06 p vcc3 p04 o gnt0# y02 io stop# ac26 o ds0# a05 i sba3 d09 io hd44# h21 p vcc3 p05 p gnd y03 io serr# ad01 io ad03 a06 i sba0 d10 io hd43# h22 io ha16 p11 p gnd y04 io ad13 ad02 io ad00 a07 o init# d11 io hd32# h23 io ha07 p12 p gnd y05 io cbe1# ad03 p gnd a08 io hd58# d12 i gtlref h24 p vcc3 p13 p gnd y06 p gnd ad04 io md63 a09 io hd53# d13 io hd35# h25 io ha05 p14 p gnd y21 p gnd ad05 io md60 a10 io hd63# d14 o mclko h26 io ha03 p15 p gnd y22 io md47 ad06 i suclk a11 io hd54# d15 io hd26# j01 io gd07 p16 p gnd y23 io md45 ad07 io md56 a12 io hd57# d16 i mclki j02 io gd08 p22 p gnd y24 io md14 ad08 p vcc3 a13 p gnd d17 io hd27# j03 io gd09 p23 io md00 y25 io md46 ad09 io md49 a14 io hd47# d18 io hd19# j04 io gd15 p24 p gnd y26 io md15 ad10 io md16 a15 io hd45# d19 io hd11# j05 io gdsel# p25 io md02 aa01 io ad15 ad11 io mecc2 / cke2# a16 io hd34# d20 io hd09# j06 p vcc3 p26 io md34 aa02 io ad14 ad12 io mecc3 / cke3# a17 io hd33# d21 io hd03# j 21 p vcc3 r01 ioad30 aa03ioad11 ad13 p gnd a18 io hd29# d22 o cpurst# j22 io ha10 r02 io ad29 aa04 io ad12 ad14 o maa9 a19 io hd24# d23 i gtlref j23 io ha08 r03 io ad28 aa05 io ad08 ad15 o mab5 a20 io hd23# d24 io ha28 j24 io ha09 r04 i re q 4# aa06 p gnd ad16 o swed# / mwed# a21 io hd20# d25 io ha22 j25 io ha04 r05 o gnt4# aa07 p vcc3 ad17 o ras4# / cs4# a22 io hd10# d26 io ha20 j26 io bnr# r11 p vcc3 aa08 p vcc3 ad18 o mab8 a23 io hd06# e01 io gd18 k01 io gd06 r12 p gnd aa09 p vcc3 ad19 p vcc3 a24 io hd05# e02 io gd19 k02 io gd05 r13 p gnd aa10 io md22 ad20 o maa7 a25 io hd01# e03 io gd21 k03 io gds0# r14 p gnd aa17 p 5vref ad21 o maa0 a26 p gnd e04 io gd22 k04 io gd14 r15 p gnd aa18 p vcc3 ad22 p mvref b01 io gd27 e05 p gnd k05 io gbe1# r16 p vcc3 aa19 p vcc3 ad23 o maa4 b02 io gd30 e06 o st0 k06 io gd12 r22 io md01 aa20 p vcc3 ad24 p gnd b03 i sba7 e07 o st1 k21 p vtt r23 io md32 aa21 p gnd ad25 o ds5# b04 i sba4 e08 io hd41# k22 io ha06 r24 io md03 aa22 io mecc0 / cke0# ad26 o ds4# b05 i sba2 e09 io hd40# k23 io hre q 1# r25 io md35 aa23 io mecc4 / cke4# ae01 io ad04 b06 i grbf# e10 i gclk k24 io hre q 0# r26 io md04 aa24 io mecc5 / cke5# ae02 io ad01 b07 i gre q # e11 p agnd k25 io bpri# t01 io ad27 aa25 o swec# / mwec# ae03 o pgnt# b08 io hd61# e12 p vtt k26 io hre q 4# t02 io ad25 aa26 o ras0# / cs0# ae04 io md62 b09 io hd50# e13 p gnd l01 io gd03 t03 io ad24 ab01 io ad10 ae05 io md29 b10 io hd56# e14 p gnd l02 io gd02 t04 io ad26 ab02 io ad09 ae06 io md59 b11 io hd60# e15 p avcc l03 io gd04 t05 i pclk ab03 io ad07 ae07 io md25 b12 io hd52# e16 i hclk l04 io gd01 t11 p gnd ab04 io cbe0# ae08 io md53 b13 io hd51# e17 p agnd l05 io gbe0# t12 p vcc3 ab05 p gnd ae09 io md20 b14 io hd42# e18 io hd21# l11 p gnd t13 p gnd ab06 i sust# ae10 io md48 b15 io hd39# e19 io hd17# l12 p vcc3 t14 p gnd ab07 io md58 ae11 io mecc6 / cke6# b16 io hd37# e20 io hd07# l13 p gnd t15 p vcc3 ab08 p vsus ae12 o mab12 b17 io hd28# e21 io hd02# l14 p gnd t16 p gnd ab09 io md23 ae13 o srasd# b18 io hd30# e22 p gnd l15 p vcc3 t22 iomd06 ab10 iomd51 ae14 o maa10 b19 io hd22# e23 o bre q 0# l16 p gnd t23 iomd33 ab11 iomd19 ae15 o maa12 b20 io hd18# e24 io ha23 l22 io htrdy# t24 io md36 ab12 io md18 ae16 o mab9 b21 io hd13# e25 io ha25 l23 io drdy# t25 io md05 ab13 p gnd ae17 o ras3# / cs3# b22 io hd12# e26 io ha19 l24 io defer# t26 io md37 ab14 p gnd ae18 o ras6# / cs6# b23 io hd08# f01 io gtrdy# l25 i hlock# u01 io cbe3# ab15 o ds3# ae19 o mab3 b24 iohd00# f02 iogfrm# l26 iohre q 2# u02 io ad21 ab16 o cas2# / d q m2# ae20 o maa8 b25 io ha30 f03 io gd17 m01 i re q 3# u03 io ad20 ab17 o cas6# / d q m6# ae21 o maa1 b26 io ha29 f04 io gd16 m02 o gnt2# u04 io ad23 ab18 o ras5# / cs5# ae22 o ras2# / cs2# c01 io gd28 f05 io gbe3# m03 i re q 2# u05 io ad22 ab19 o scasd# ae23 o cas0# / d q m0# c02 io gd31 f06 p gnd m04 io lock# u06 p 5vref ab20 o maa13 ae24 o maa6 c03 p gnd f07 p vcc3 m05 io gd00 u21 p vsus ab21 o mab0 ae25 o srasc# c04 i sbs# f08 p vcc3 m11 p vcc3 u22 io md07 ab22 p gnd ae26 o srasb# c05 i sba1 f09 p vcc3 m12 p gnd u23 io md38 ab23 io mecc1 / cke1# af01 p gnd c06 i gpipe# f10 p avcc m13 p gnd u24 io md08 ab24 o swea# / mwea# af02 io ad02 c07 o ggnt# f17 p vtt m14 p gnd u25 io md40 ab25 o scasa# af03 i pre q # c08 p vcc3 f18 p vcc3 m15 p gnd u26 io md09 ab26 o cas4# / d q m4# af04 io md31 c09 io hd48# f19 p vcc3 m16 p vcc3 v01 io ad19 ac01 io ad06 af05 io md61 c10 io hd62# f20 p vcc3 m22 io hre q 3# v02 io ad16 ac02 io ad05 af06 io md28 c11 io hd55# f21 p gnd m23 io rs2# v03 io cbe2# ac03 i reset# af07 io md57 c12 io hd59# f22 io ha24 m24 io rs0# v04 io ad18 ac04 i crsti# af08 io md24 c13 iohd46# f23 ioha27 m25 i hitm# v05 ioad17 ac05iomd30 af09 iomd52 c14 p gnd f24 io ha15 m26 io hit# v06 p vcc3 ac06 io md27 af10 io md17 c15 io hd36# f25 io ha18 n01 o gnt1# v21 p vcc3 ac07 io md26 af11 io mecc7 / cke7# c16 io hd38# f26 io ha11 n02 i re q 1# v22 io md11 ac08 io md55 af12 o mab13 c17 io hd31# g01 io gd13 n03 p gnd v23 io md39 ac09 io md21 af13 o mab11 c18 io hd25# g02 io gpar / gckr# n04 o gnt3# v24 io md41 ac10 io md54 af14 p gnd c19 p vcc3 g03 io gstop# n05 p gnd v25 io md10 ac11 io md50 af15 o maa5 c20 io hd16# g04 io gd20 n11 p gnd v26 io md42 ac12 p mvref af16 o mab4 c21 io hd15# g05 io gbe2# n12 p gnd w01 io frame# ac13 o ds7# af17 o sweb# / mweb# c22 io hd14# g06 p gnd n13 p gnd w02 io irdy# ac14 o ds6# af18 o ras7# / cs7# c23 io hd04# g21 p gnd n14 p gnd w03 p vcc3 ac15 o maa2 af19 o mab6 c24 p gnd g22 io ha17 n15 p gnd w04 io trdy# ac16 o ds2# af20 o mab2 c25 io ha26 g23 io ha21 n16 p gnd w05 io par ac17 o cas3# / d q m3# af21 o srasa# c26 io ha31 g24 io ha13 n22 p gnd w06 p vcc3 ac18 o cas7# / d q m7# af22 o cas5# / d q m5# d01 io gd25 g25 io ha12 n23 io ads# w21 p vcc3 ac19 o mab10 af23 o cas1# / d q m1# d02 io gd24 g26 io ha14 n24 io dbsy# w22 io md13 ac20 o mab7 af24 o scasb# d03 io gd26 h01 io gd10 n25 io rs1# w23 io md43 ac21 o maa11 af25 o mab1 d04 p gvref h02 io gd11 n26 p gnd w24 p vcc3 ac22 o maa3 af26 p gnd
VT82C691 preliminary revision 1.0 july 16, 1998 - 8- pinouts C VT82C691 apollo pro 7hfkqrorjlhv ,qf : h& : h&r rqqhfw qqhfw figure 4. VT82C691 pin list (alphabetical order) pin # pin name pin # pin name pin # pin name pin # pin name pin # pin names pin # pin name u06 p 5vref j02 io gd08 aa06 p gnd c18 io hd25# r22 io md01 ab18 o ras5# / cs5# aa17 p 5vref j03 io gd09 aa21 p gnd d15 io hd26# p25 io md02 ae18 o ras6# / cs6# ad02 io ad00 h01 io gd10 ab05 p gnd d17 io hd27# r24 io md03 af18 o ras7# / cs7# ae02 io ad01 h02 io gd11 ab13 p gnd b17 io hd28# r26 io md04 p02 i re q 0# af02 io ad02 k06 io gd12 ab14 p gnd a18 io hd29# t25 io md05 n02 i req1# ad01 io ad03 g01 io gd13 ab22 p gnd b18 io hd30# t22 io md06 m03 i req2# ae01 io ad04 k04 io gd14 ad03 p gnd c17 io hd31# u22 io md07 m01 i req3# ac02 io ad05 j04 io gd15 ad13 p gnd d11 io hd32# u24 io md08 r04 i req4# ac01 io ad06 f04 io gd16 ad24 p gnd a17 io hd33# u26 io md09 ac03 i reset# ab03 io ad07 f03 io gd17 af01 p gnd a16 io hd34# v25 io md10 m24 io rs0# aa05 io ad08 e01 io gd18 af14 p gnd d13 io hd35# v22 io md11 n25 io rs1# ab02 io ad09 e02 io gd19 af26 p gnd c15 io hd36# w25 io md12 m23 io rs2# ab01 io ad10 g04 io gd20 p04 o gnt0# b16 io hd37# w22 io md13 a06 i sba0 aa03 io ad11 e03 io gd21 n01 o gnt1# c16 io hd38# y24 io md14 c05 i sba1 aa04 io ad12 e04 io gd22 m02 o gnt2# b15 io hd39# y26 io md15 b05 i sba2 y04 io ad13 d05 io gd23 n04 o gnt3# e09 io hd40# ad10 io md16 a05 i sba3 aa02 io ad14 d02 io gd24 r05 o gnt4# e08 io hd41# af10 io md17 b04 i sba4 aa01 io ad15 d01 io gd25 g02 io gpar/gckr# b14 io hd42# ab12 io md18 a04 i sba5 v02 io ad16 d03 io gd26 c06 i gpipe# d10 io hd43# ab11 io md19 a03 i sba6 v05 io ad17 b01 io gd27 b06 i grbf# d09 io hd44# ae09 io md20 b03 i sba7 v04 io ad18 c01 io gd28 b07 i gre q # a15 io hd45# ac09 io md21 c04 i sbs# v01 io ad19 a02 io gd29 h04 io gserr#/pckr# c13 io hd46# aa10 io md22 ab25 o scasa# u03 io ad20 b02 io gd30 g03 io gstop# a14 io hd47# ab09 io md23 af24 o scasb# u02 io ad21 c02 io gd31 d12 i gtlref c09 io hd48# af08 io md24 ac25 o scasc# u05 io ad22 k03 io gds0# d23 i gtlref d08 io hd49# ae07 io md25 ab19 o scasd# u04 io ad23 d06 io gds1# f01 io gtrdy# b09 io hd50# ac07 io md26 y03 io serr# t03 io ad24 j05 io gdsel# d04 p gvref b13 io hd51# ac06 io md27 af21 o srasa# t02 io ad25 f02 io gfrm# h26 io ha03 b12 io hd52# af06 io md28 ae26 o srasb# t04 io ad26 c07 o ggnt# j25 io ha04 a09 io hd53# ae05 io md29 ae25 o srasc# t01 io ad27 h05 io girdy# h25 io ha05 a11 io hd54# ac05 io md30 ae13 o srasd# r03 io ad28 a01 p gnd k22 io ha06 c11 io hd55# af04 io md31 e06 o st0 r02 io ad29 a13 p gnd h23 io ha07 b10 io hd56# r23 io md32 e07 o st1 r01 io ad30 a26 p gnd j23 io ha08 a12 io hd57# t23 io md33 d07 o st2 p03 io ad31 c03 p gnd j24 io ha09 a08 io hd58# p26 io md34 y02 io stop# n23 io ads# c14 p gnd j22 io ha10 c12 io hd59# r25 io md35 ab06 i sust# e11 p agnd c24 p gnd f26 io ha11 b11 io hd60# t24 io md36 ad06 i suclk e17 p agnd e05 p gnd g25 io ha12 b08 io hd61# t26 io md37 ab24 o swea# / mwea# e15 p avcc e13 p gnd g24 io ha13 c10 io hd62# u23 io md38 af17 o sweb# / mweb# f10 p avcc e14 p gnd g26 io ha14 a10 io hd63# v23 io md39 aa25 o swec# / mwec# j26 io bnr# e22 p gnd f24 io ha15 m26 io hit# u25 io md40 ad16 o swed# / mwed# k25 io bpri# f06 p gnd h22 io ha16 m25 i hitm# v24 io md41 w04 io trdy# e23 o bre q 0# f21 p gnd g22 io ha17 l25 i hlock# v26 io md42 c08 p vcc3 ae23 o cas0# / d q m0# g06 p gnd f25 io ha18 k24 io hre q 0# w23 io md43 c19 p vcc3 af23 o cas1# / dqm1# g21 p gnd e26 io ha19 k23 io hreq1# w26 io md44 f07 p vcc3 ab16 o cas2# / dqm2# l11 p gnd d26 io ha20 l26 io hreq2# y23 io md45 f08 p vcc3 ac17 o cas3# / dqm3# l13 p gnd g23 io ha21 m22 io hreq3# y25 io md46 f09 p vcc3 ab26 o cas4# / dqm4# l14 p gnd d25 io ha22 k26 io hreq4# y22 io md47 f18 p vcc3 af22 o cas5# / d q m5# l16 p gnd e24 io ha23 l22 io htrdy# ae10 io md48 f19 p vcc3 ab17 o cas6# / d q m6# m12 p gnd f22 io ha24 a07 o init# ad09 io md49 f20 p vcc3 ac18 o cas7# / d q m7# m13 p gnd e25 io ha25 w02 io irdy# ac11 io md50 h03 p vcc3 ab04 io cbe0# m14 p gnd c25 io ha26 m04 io lock# ab10 io md51 h06 p vcc3 y05 io cbe1# m15 p gnd f23 io ha27 ad21 o maa0 af09 io md52 h21 p vcc3 v03 io cbe2# n03 p gnd d24 io ha28 ae21 o maa1 ae08 io md53 h24 p vcc3 u01 io cbe3# n05 p gnd b26 io ha29 ac15 o maa2 ac10 io md54 j06 p vcc3 d22 o cpurst# n11 p gnd b25 io ha30 ac22 o maa3 ac08 io md55 j 21 p vcc3 ac04 i crsti# n12 p gnd c26 io ha31 ad23 o maa4 ad07 io md56 l12 p vcc3 n24 io dbsy# n13 p gnd e16 i hclk af15 o maa5 af07 io md57 l15 p vcc3 l24 io defer# n14 p gnd b24 io hd00# ae24 o maa6 ab07 io md58 m11 p vcc3 y01 io devsel# n15 p gnd a25 io hd01# ad20 o maa7 ae06 io md59 m16 p vcc3 l23 io drdy# n16 p gnd e21 io hd02# ae20 o maa8 ad05 io md60 r11 p vcc3 ac26 o ds0# n22 p gnd d21 io hd03# ad14 o maa9 af05 io md61 r16 p vcc3 ac23 o ds1# n26 p gnd c23 io hd04# ae14 o maa10 ae04 io md62 t12 p vcc3 ac16 o ds2# p01 p gnd a24 io hd05# ac21 o maa11 ad04 io md63 t15 p vcc3 ab15 o ds3# p05 p gnd a23 io hd06# ae15 o maa12 aa22 io mecc0/cke0# v06 p vcc3 ad26 o ds4# p11 p gnd e20 io hd07# ab20 o maa13 ab23 io mecc1/cke1# v21 p vcc3 ad25 o ds5# p12 p gnd b23 io hd08# ab21 o mab0 ad11 io mecc2/cke2# w03 p vcc3 ac14 o ds6# p13 p gnd d20 io hd09# af25 o mab1 ad12 io mecc3/cke3# w06 p vcc3 ac13 o ds7# p14 p gnd a22 io hd10# af20 o mab2 aa23 io mecc4/cke4# w21 p vcc3 w01 io frame# p15 p gnd d19 io hd11# ae19 o mab3 aa24 io mecc5/cke5# w24 p vcc3 l05 io gbe0# p16 p gnd b22 io hd12# af16 o mab4 ae11 io mecc6/cke6# aa07 p vcc3 k05 io gbe1# p22 p gnd b21 io hd13# ad15 o mab5 af11 io mecc7/cke7# aa08 p vcc3 g05 io gbe2# p24 p gnd c22 io hd14# af19 o mab6 ac12 p mvref aa09 p vcc3 f05 io gbe3# r12 p gnd c21 io hd15# ac20 o mab7 ad22 p mvref aa18 p vcc3 e10 i gclk r13 p gnd c20 io hd16# ad18 o mab8 w05 io par aa19 p vcc3 m05 io gd00 r14 p gnd e19 io hd17# ae16 o mab9 t05 i pclk aa20 p vcc3 l04 io gd01 r15 p gnd b20 io hd18# ac19 o mab10 ae03 o pgnt# ad08 p vcc3 l02 io gd02 t11 p gnd d18 io hd19# af13 o mab11 af03 i preq# ad19 p vcc3 l01 io gd03 t13 p gnd a21 io hd20# ae12 o mab12 aa26 o ras0# / cs0# u21 p vsus l03 io gd04 t14 p gnd e18 io hd21# af12 o mab13 ac24 o ras1# / cs1# ab08 p vsus k02 io gd05 t16 p gnd b19 io hd22# d16 i mclki ae22 o ras2# / cs2# e12 p vtt k01 io gd06 y06 p gnd a20 io hd23# d14 o mclko ae17 o ras3# / cs3# f17 p vtt j01 io gd07 y21 p gnd a19 io hd24# p23 io md00 ad17 o ras4# / cs4# k21 p vtt
VT82C691 preliminary revision 1.0 july 16, 1998 - 9- pinouts C VT82C691 apollo pro 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw p in d escriptions table 1. VT82C691 pin descriptions cpu interface signal name pin # i/o signal description ads# n23 b address strobe . the cpu asserts ads# in t1 of the cpu bus cycle. bnr# j26 b block next request . used to block the current request bus owner from issuing new requests. this signal is used to dynamically control the processor bus pipeline depth. bpri# k25 b priority agent bus request . the owner of this signal will always be the next bus owner. this signal has priority over symmetric bus requests and causes the current symmetric owner to stop issuing new transactions unless the hlock# signal is asserted. the VT82C691 drives this signal to gain control of the processor bus. dbsy# n24 b data bus busy . used by the data bus owner to hold the data bus for transfers requiring more than one cycle. defer# l24 b defer . the VT82C691 uses a dynamic deferring policy to optimize system performance. the VT82C691 also uses the defer# signal to indicate a processor retry response. drdy# l23 b data ready . asserted for each cycle that data is transferred. hit# m26 b hit . indicates that a cacheing agent holds an unmodified version of the requested line. also driven in conjunction with hitm# by the target to extend the snoop window. hitm# m25 i hit modified . asserted by the cpu to indicate that the address presented with the last assertion of eads# is modified in the l1 cache and needs to be written back. hlock# l25 i host lock . all cpu cycles sampled with the assertion of hlock# and ads# until the negation of hlock# must be atomic. hreq[4:0]# k26, m22, l26, k23, k24 b request command . asserted during both clocks of the request phase. in the first clock, the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. in the second clock, the signals carry additional information to define the complete transaction type. htrdy# l22 b host target ready . indicates that the target of the processor transaction is able to enter the data transfer phase. rs[2:0]# m23, n25, m24 b response signals . indicates the type of response per the table below: rs[2:0]# response type 000 idle state 001 retry response 010 defer response 011 reserved 100 hard failure 101 normal without data 110 implicit writeback 111 normal with data cpurst# d22 o cpu reset. reset output to cpu init# a7 o init. init output to cpu. breq0# e23 o bus request 0. bus request output to cpu.
VT82C691 preliminary revision 1.0 july 16, 1998 - 10- pinouts C VT82C691 apollo pro 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw cpu interface (continued) signal name pin # i/o signal description ha[31:3] (see pinout tables) b host address bus. ha[31:3] connect to the address bus of the host cpu. during cpu cycles ha[31:3] are inputs. these signals are driven by the VT82C691 during cache snooping operations. hd[63:0]# (see pinout tables) b host cpu data. these signals are connected to the cpu data bus. gtlref d12, d23 p gtl + reference voltage . this is the reference voltage derived from the termination voltage to the pullup resistors and determines the noise margin for the signals. this signal goes to the reference input of the gtl + sense amp on each gtl + input or i/o pin. note: clocking of the cpu and cache interfaces is performed with hclk. see the clock pin group at the end of the pin descriptions section for descriptions of the clock input pins. note: the VT82C691 pinouts were defined assuming the atx pcb layout model shown below (and general pin layout shown) as a guide for pcb component placement. other pcb layouts (at, lpx, and nlx) were also considered and can typically follow the same general component placement. dram modules slot-1 cpu ide connectors isa slots pci slots agp slot vt82c 596 south bridge power supply cpu dram pci agp 691 a af 1 26
VT82C691 preliminary revision 1.0 july 16, 1998 - 11- pinouts C VT82C691 apollo pro 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw dram interface signal name pin # i/o signal description md[63:0] (see pinout tables) b memory data. these signals are connected to the dram data bus. note: md0 is internally pulled up for use in edo memory type detection. mecc[7:0] / cke[7:0] af11, ae11, aa24, aa23, ad12, ad11, ab23, aa22 b multifunction pins 1. dram ecc or ec data (rx78[0]=0) 2. clock enables. clock enables for each dram bank (rx78[0]=1) for powering down the sdrams in notebook applications. 3. strap options: (strap pin low for 0 or high for 1 using 4.7k ohm) mecc0 rx68[0] cpu frequency (0 = 66 mhz, 100 mhz) mecc2 rx69[2] dram frequency (0 = cpu, 1 = agp) maa[13:0] ab20, ae15, ac21, ae14, ad14, ae20, ad20, ae24, af15, ad23, ac22, ac15, ae21, ad21 o memory address a. dram address lines (two sets for better drive) mab[13:0] af12, ae12, af13, ac19, ae16, ad18, ac20, af19, ad15, af16, ae19, af20, af25, ab21 o memory address b. dram address lines (two sets for better drive) ras[7:0]# / cs[7:0]# af18, ae18, ab18, ad17, ae17, ae22, ac24, aa26 o multifunction pins 1. fpg/edo dram: row address strobe of each bank. 2. synchronous dram: chip select of each bank.. cas[7:0]# / dqm[7:0]# ac18, ab17, af22, ab26, ac17, ab16, af23, ae23 o multifunction pins 1. fpg/edo dram: column address strobe of each byte lane. 2. synchronous dram: data mask of each byte lane. srasa#, srasb#, srasc#, srasd# af21 ae26 ae25 ae13 o row address command indicator. for support of up to four synchronous dram dimm slots (these are not copies as each dimm slot may have separate timing). a controls banks 0-1 (module 0), b controls banks 2-3 (module 1), c controls banks 4-5 (module 2), and d controls banks 6-7 (module 3). scasa#, scasb#, scasc#, scasd# ab25 af24 ac25 ab19 o column address command indicator. for support of up to three synchronous dram dimm slots (these are not copies as each dimm slot may have separate timing). a controls banks 0-1 (module 0), b controls banks 2-3 (module 1), c controls banks 4-5 (module 2), and d controls banks 6-7 (module 3). swea# / mwea#, sweb# / mweb#, swec# / mwec#, swed# / mwed# ab24 af17 aa25 ad16 o write enable command indicator. for support of up to three synchronous dram dimm slots (these are not copies as each dimm slot may have separate timing). multifunction pins, used as mwe# pins for fpg/edo memory. a controls banks 0-1 (module 0), b controls banks 2-3 (module 1), c controls banks 4-5 (module 2), and d controls banks 6-7 (module 3). ds[7:0]# ac13, ac14, ad25, ad26, ab15, ac16, ac23, ac26 o ddr sdram data strobes. every 8 data bits share one common data strobe. i.e., ds0# corresponds to md[7:0], ds1# corresponds to md[15:0], etc..
VT82C691 preliminary revision 1.0 july 16, 1998 - 12- pinouts C VT82C691 apollo pro 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw pci bus interface signal name pin # i/o signal description frame# w1 b frame. assertion indicates the address phase of a pci transfer. negation indicates that one more data transfer is desired by the cycle initiator. ad[31:0] (see pinout tables) b address/data bus. the standard pci address and data lines. the address is driven with frame# assertion and data is driven or received in following cycles. cbe[3:0]# u1, v3, y5, ab4 b command/byte enable. commands are driven with frame# assertion. byte enables corresponding to supplied or requested data are driven on following clocks. irdy# w2 b initiator ready. asserted when the initiator is ready for data transfer. trdy# w4 b target ready. asserted when the target is ready for data transfer. stop# y2 b stop. asserted by the target to request the master to stop the current transaction. devsel# y1 b device select. this signal is driven by the VT82C691 when a pci initiator is attempting to access main memory. it is an input when the VT82C691 is acting as a pci initiator. par w5 b parity. a single parity bit is provided over ad[31:0] and c/be[3:0]. serr# y3 b system error. VT82C691 will pulse this signal when it detects a system error condition. lock# m4 b lock. used to establish, maintain, and release resource lock. preq# af3 i south bridge request. this signal comes from the south bridge. preq# is the south bridge request for the pci bus. pgnt# ae3 o south bridge grant. this signal driven by the VT82C691 to grant pci access to the south bridge. req[4:0]# r4, m1, m3, n2, p2 i pci master request. pci master requests for pci. gnt[4:0]# r5, n4, m2, n1, p4 o pci master grant. permission is given to the master to use pci. note: clocking of the pci interface is performed with pclk; see the clock pin group at the end of the pin descriptions sectio n for descriptions of the clock input pins.
VT82C691 preliminary revision 1.0 july 16, 1998 - 13- pinouts C VT82C691 apollo pro 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw agp bus interface signal name pin # i/o signal description gfrm# f2 b frame (pci transactions only). assertion indicates the address phase of a pci transfer. negation indicates that one more data transfer is desired by the cycle initiator. gds0# k3 b bus strobe 0 (agp transactions only). provides timing for 2x data transfer mode on ad[15:0]. the agent that is providing the data drives this signal. gds1# d6 b bus strobe 1 (agp transactions only). provides timing for 2x data transfer mode on ad[31:16]. the agent that is providing the data drives this signal. gd[31:0] (see pinout tables) b address/data bus. the standard agp/pci address and data lines. the address is driven with gds0# and gds1# assertion for agp transfers and is driven with gfrm# assertion for pci transfers. gbe[3:0]# f5, g5, k5, l5 b command/byte enable. agp: these pins provide command information (different commands than for pci) driven by the master (graphics controller) when requests are being enqueued using pipe#. these pins provide valid byte information during agp write transactions and are driven by the master. the target (this chip) drives these lines to "0000" during the return of agp read data, but the state of these pins is ignored by the agp master. pci: commands are driven with gfrm# assertion. byte enables corresponding to supplied or requested data are driven on following clocks. girdy# h5 b initiator ready agp: for write operations, the assertion of this pin indicates that the master is ready to provide all write data for the current transaction. once this pin is asserted, the master is not allowed to insert wait states. for read operations, the assertion of this pin indicates that the master is ready to transfer a subsequent block of read data. the master is never allowed to insert a wait state during the initial block of a read transaction. however, it may insert wait states after each block transfers. pci: asserted when the initiator is ready for data transfer. gtrdy# f1 b target ready: agp: indicates that the target is ready to provide read data for the entire transaction (when the transaction can complete within four clocks) or is ready to transfer a (initial or subsequent) block of data when the transfer requires more than four clocks to complete. the target is allowed to insert wait states after each block transfers on both read and write transactions. pci: asserted when the target is ready for data transfer. gstop# g3 b stop (pci transactions only). asserted by the target to request the master to stop the current transaction. gdsel# j5 b device select (pci transactions only). this signal is driven by the VT82C691 when a pci initiator is attempting to access main memory. it is an input when the VT82C691 is acting as pci initiator. not used for agp cycles. note: clocking of the agp interface is performed with gclk; see the clock pin group for descriptions of the clock input pins. note: pcb layout guidelines (reference from agp specification) 1. total motherboard trace length 10 max, trace impedance = 65 ohms 15 ohms, minimize signal crosstalk 2. trace lengths within groups matched to within 2 inches or better groups are: a. gds0#, gd15-0, gbe1-0# b. gds1#, gd31-16, gbe3-2# c. sbs#, sba7-0 3. ground isolation should be provided around gds0# and gds1# to prevent crosstalk with gd[31:0]. ideally ground traces should be provided adjacent to gdsn# on the same signal layer, but at a minimum wider spaces should be provided on either side (e.g., 16 mil spaces on either side of gdsn# if gdsn# signal traces are 8 mil).
VT82C691 preliminary revision 1.0 july 16, 1998 - 14- pinouts C VT82C691 apollo pro 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw agp bus interface (continued) signal name pin # io signal description gpipe# c6 i pipelined request. asserted by the master (graphics controller) to indicate that a full- width request is to be enqueued by the target VT82C691. the master enqueues one request each rising edge of gclk while pipe# is asserted. when pipe# is deasserted no new requests are enqueued across the ad bus. grbf# b6 i read buffer full. indicates if the master (graphics controller) is ready to accept previously requested low priority read data. when rbf# is asserted, the VT82C691 will not return low priority read data to the master. sba[7:0] b3, a3, a4, b4, a5, b5, c5, a6 i sideband address. provides an additional bus to pass address and command information from the master (graphics controller) to the target (the VT82C691). these pins are ignored until enabled. sbs# c4 i sideband strobe. provides timing for sba[7:0] (driven by the master) st[2:0] d7, e7, e6 o status (agp only). provides information from the arbiter to a master to indicate what it may do. only valid while ggnt# is asserted. 000 indicates that previously requested low priority read or flush data is being returned to the master (graphics controller). 001 indicates that previously requested high priority read data is being returned to the master. 010 indicates that the master is to provide low priority write data for a previously enqueued write command. 011 indicates that the master is to provide high priority write data for a previously enqueued write command. 100 reserved. (arbiter must not issue, may be defined in the future). 101 reserved. (arbiter must not issue, may be defined in the future). 110 reserved. (arbiter must not issue, may be defined in the future). 111 indicates that the master (graphics controller) has been given permission to start a bus transaction. the master may enqueue agp requests by asserting pipe# or start a pci transaction by asserting gfrm#. st[2:0] are always outputs from the VT82C691 and inputs to the master. greq# b7 i request. master request for agp. ggnt# c7 o grant. permission is given to the master to use agp. gpar / gckrun# g2 io o rx78[1]=0: agp parity. a single parity bit is provided over gd[31:0] and gbe[3:0]. rx78[1]=1: agp clock run. used to stop the agp bus clock to reduce bus power usage. gserr# / pckrun# h4 io o rx78[1]=0: agp system error. the VT82C691 will pulse this signal when it detects a system error condition. rx78[1]=1: pci clock run . used to stop the pci bus clock to reduce bus power usage. note: for pci operation on the agp bus, the following pins are not required: - perr# (parity and error reporting not required on transient data devices such as graphics controllers) - lock# (no lock requirement on agp) - idsel (internally connected to ad16 on agp-compliant masters) note: separate system interrupts are not provided for agp. the agp connector provides interrupts via pci bus inta-b#. note: the agp bus supports only one master directly (req[3:0]# and gnt[3:0]# are not provided). external logic is required to i mplement additional master capability. note that the arbitration mechanism on the agp bus is different from the pci bus. note: a separate reset is not required for the agp bus (reset# resets both pci and agp buses) note: two mechanisms are provided by the agp bus to enqueue master requests: pipe# (to send addresses multiplexed on the ad lin es) and the sba port (to send addresses unmultiplexed). agp masters implement one or the other or select one at initialization time (t hey are not allowed to change during runtime). therefore only one of the two will be used and the signals associated with the other will n ot be used. therefore the 691 has an internal pullup on rbf# to maintain it in the de-asserted state in case it is not implemented on the m aster device.
VT82C691 preliminary revision 1.0 july 16, 1998 - 15- pinouts C VT82C691 apollo pro 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw clock / reset control signal name pin # i/o signal description hclk e16 i host clock. this pin receives the host cpu clock. this clock is used by all VT82C691 logic that is in the host cpu domain. the memory interface logic will also use this clock if selected (memory system timing can alternately be selected to use the agp bus clock). the cpu clock must lead the agp clock by 0.2 0.5 nsec. mclki d16 i memory clock in. mclko d14 o memory clock out. gclk e10 i agp clock. this pin receives the agp bus clock. this clock is used by all VT82C691 logic that is in the agp clock domain. the agp clock must be synchronous / pseudo- synchronous to the host cpu clock (selectable as shown in the table below). the cpu clock must lead the agp clock by 0.2 0.5 nsec. pclk t5 i pci clock. this pin receives a buffered host clock divided-by-2 or 3. see strapping option on mecc0 (strapping options can be read back in configuration register 68). this clock is used by all of the VT82C691 logic that is in the pci clock domain. this clock input must be 33 mhz maximum to comply with pci specification requirements and must be synchronous with the host cpu clock, hclk, with an hclk:pclk frequency ratio of 2:1 or 3:1 as shown in the table below. the host cpu clock must lead the pci clock by 1.5 0.5 nsec. typical clock frequency combinations rx68[0] mode host clock agp clock pci clock 0 2x 66 mhz 66 mhz 33 mhz 1 3x 100 mhz 66 mhz 33 mhz reset# ac3 i reset. input from south bridge chip. when asserted, this signal resets the VT82C691 and sets all register bits to the default value. the same signal that connects to this pin may also be used (connected through an external inverter) to reset the isa bus (if implemented). the rising edge of this signal is used to sample all power-up strap options (see ha25-27). crsti# ac4 i cpu reset in. cpu reset input from south bridge chip. cpurst# d22 o cpu reset. cpu reset output to cpu. init# a7 o cpu init. init output to cpu susclk ad6 i suspend clock. for implementation of the suspend-to-dram feature. ground this pin to disable. sustat# ab6 i suspend status. for implementation of the suspend-to-dram feature. connect to an external pullup to disable. gckrun# / gpar g2 o io agp clock run (rx78[1]=1). for implementation of agp bus clock control for very low-power agp bus operation. refer to the agp specification for additional information. pckrun# / gserr# h4 o io pci clock run (rx78[1]=1). for implementation of pci bus clock control for very low- power pci bus operation. refer to the pci mobile design guidelines document for additional information.
VT82C691 preliminary revision 1.0 july 16, 1998 - 16- pinouts C VT82C691 apollo pro 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw power and ground signal name pin # i/o signal description vcc3 c8, c19, f7-9, f18- f20, h3, h6, h21, h24, j6, j21, l12, l15, m11, m16, r11, r16, t12, t15, v6, v21, w3, w6, w21, w24, aa7-aa9, aa18-aa20, ad8, ad19 p power for internal logic (3.3v 5%). vsus u21, ab8 p suspend power (3.3v 5%). power for swea-d#, ras[7-0]#, cas[7- 0]#, sustat#, susclk, cke[7:0]#. gnd a1, a13, a26, c3, c14, c24, e5, e13- e14, e22, f6, f21, g6, g21, l11, l13- l14, l16, m12-m15, n3, n5, n11-n16, n22, n26, p1, p5, p11-16, p22, p24, r12-r15, t11, t13- t14, t16, y6, y21, aa6, aa21, ab5, ab13-ab14, ab22, ad3, ad13, ad24, af1, af14, af26 p ground avcc e15, f10 p analog power (3.3v 5%). for internal clock logic. agnd e11, e17 p analog ground. for internal clock logic. connect to main ground plane. vtt e12, f17, k21 p cpu interface termination voltage (1.5v 10%). gtlref d12, d23 p cpu interface gtl+ voltage reference. 2/3 vtt 2% 5vref u6, aa17 p 5v reference (5v 5%). used to provide 5v input tolerance. mvref ac12, ad22 p dram voltage reference. 1.5v for sdr sdram, 1.0v for ddr sdram (5%) gvref d4 p agp voltage reference. 0.39 gvcc to 0.41 gvcc. typical value is 1.32v (0.40 times 3.3v). this can be provided with a resistive divider on gvcc using 270 ohm and 180 ohm (2%) resistors.
VT82C691 preliminary revision 1.0 july 16, 1998 - 17- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw r egisters register overview the following tables summarize the configuration and i/o registers of the VT82C691. these tables also document the power-on default value (default) and access type (acc) for each register. access type definitions used are rw (read/write), ro (read/only), for reserved / used (essentially the same as ro), and rwc (or just wc) (read / write 1s to clear individual bits). registers indicated as rw may have some read/only bits that always read back a fixed value (usually 0 if unused); registers designated as rwc or wc may have some read-only or read write bits (see individual register descriptions following these tables for details). all offset and default values are shown in hexadecimal unless otherwise indicated. table 2. VT82C691 registers VT82C691 i/o ports port # i/o port default acc 22 pci / agp arbiter disable 00 rw cfb-8 confi g uration address 0000 0000 rw cff-c confi g uration data 0000 0000 rw
VT82C691 preliminary revision 1.0 july 16, 1998 - 18- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw VT82C691 device 0 registers - host bridge header registers offset confi g uration s p ace header default acc 1-0 vendor id 1106 ro 3-2 device id 0691 ro 5-4 command 0006 rw 7-6 status 0290 wc 8 revision id nn ro 9pro g ram interface 00 ro a sub class code 00 ro b base class code 06 ro c -reserved- ( cache line size ) 00 d latenc y timer 00 rw e header t yp e00ro f built in self test ( bist ) 00 ro 13-10 gra p hics a p erture base 0000 0008 rw 14-27 -reserved- ( base address re g isters ) 00 28-2b -reserved- ( unassi g ned ) 00 2d-2c subs y stem vendor id 0000 w1 2f-2e subs y stem id 0000 w1 33-30 -reserved- ( ex p an rom base addr ) 00 37-34 ca p abilit y pointer 0000 00a0 ro 34-3b -reserved- ( unassi g ned ) 00 3c-3d -reserved- ( interru p t line & p in ) 00 3e-3f -reserved- ( min g nt and max latenc y) 00 device-specific registers offset host cpu protocol control default acc 50 host cpu protocol control 1 00 rw 51 host cpu protocol control 2 00 rw 52 d y namic defer timer 00 rw 53-55 -reserved- ( unassi g ned ) 00 offset dram control default acc 59-58 ma ma p t yp e 0000 rw 5a-5f dram row endin g address: 5a bank 0 endin g ( ha [ 29:22 ]) 01 rw 5b bank 1 endin g ( ha [ 29:22 ]) 01 rw 5c bank 2 endin g ( ha [ 29:22 ]) 01 rw 5d bank 3 endin g ( ha [ 29:22 ]) 01 rw 5e bank 4 endin g ( ha [ 29:22 ]) 01 rw 5f bank 5 endin g ( ha [ 29:22 ]) 01 rw 56 bank 6 endin g ( ha [ 29:22 ]) 01 rw 57 bank 7 endin g ( ha [ 29:22 ]) 01 rw 60 dram t yp e00rw 61 rom shadow control c0000-cffff 00 rw 62 rom shadow control d0000-dffff 00 rw 63 rom shadow control e0000-fffff 00 rw 64 dram timin g for banks 0 , 1ecrw 65 dram timin g for banks 2 , 3ecrw 66 dram timin g for banks 4 , 5ecrw 67 dram timin g for banks 6 , 7ecrw 68 dram control 00 rw 69 dram clock select 00 rw 6a dram refresh counter 00 rw 6b dram arbitration control 01 rw 6c sdram control 00 rw 6d dram control drive stren g th 00 rw 6e ecc control 00 rw 6f ecc status 00 ro device-specific registers (continued) offset pci bus control default acc 70 pci buffer control 00 rw 71 cpu to pci flow control 1 00 rw 72 cpu to pci flow control 2 00 rw 73 pci master control 1 00 rw 74 pci master control 2 00 rw 75 pci arbitration 1 00 rw 76 pci arbitration 2 00 rw 77 chi p test ( do not p ro g ram ) 00 rw 78 pmu control 00 rw 79-7d -reserved- 00 7e-7f dll test mode ( do not p ro g ram ) 00 rw 80-ff -reserved- 00 offset gart/tlb control default acc 83-80 gart/tlb control 0000 0000 rw 84 gra p hics a p erture size 00 rw 85-87 -reserved- ( unassi g ned ) 00 8b-88 gr. a p erture translation table base 0000 0000 rw 8c-8f -reserved- ( unassi g ned ) 00 offset agp control default acc a0 agp id 02 ro a1 agp next item pointer 00 ro a2 agp s p ecification revision 10 ro a3 -reserved- ( unassi g ned ) 00 a7-a4 agp status 0700 0203 ro ab-a8 agp command 0000 0000 rw ac agp control 00 rw ad-af -reserved- ( unassi g ned ) 00 offset miscellaneous control default acc b0-ef -reserved- ( unassi g ned ) 00 f0-f7 bios scratch re g isters 00 rw f8-fb -reserved- ( unassi g ned ) 00 fd-ff reserved ( do not p ro g ram ) 0000 0000 rw
VT82C691 preliminary revision 1.0 july 16, 1998 - 19- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw VT82C691 device 1 - pci-to-pci bridge header registers offset confi g uration s p ace header default acc 1-0 vendor id 1106 ro 3-2 device id 8691 ro 5-4 command 0007 rw 7-6 status 0220 wc 8 revision id nn ro 9pro g ram interface 00 ro a sub class code 04 ro b base class code 06 ro c -reserved- ( cache line size ) 00 d latenc y timer 00 rw e header t yp e01ro f built in self test ( bist ) 00 ro 10-17 -reserved- ( base address re g isters ) 00 18 primar y bus number 00 rw 19 secondar y bus number 00 rw 1a subordinate bus number 00 rw 1b -reserved- ( secondar y latenc y timer ) 00 1c i/o base f0 rw 1d i/o limit 00 rw 1f-1e secondar y status 0000 ro 21-20 memor y base fff0 rw 23-22 memor y limit ( inclusive ) 0000 rw 25-24 prefetchable memor y base fff0 rw 27-26 prefetchable memor y limit 0000 rw 28-3d -reserved- ( unassi g ned ) 00 3f-3e pci-to-pci brid g e control 00 rw device-specific registers offset pci bus #2 control default acc 40 cpu-to-pci flow control 1 00 rw 41 cpu-to-pci flow control 2 00 rw 42 pci master control 00 rw 43-4f -reserved- ( unassi g ned ) 00
VT82C691 preliminary revision 1.0 july 16, 1998 - 20- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw miscellaneous i/o one i/o port is defined in the VT82C691: port 22. port 22 C pci arbiter disable .......................................... rw 7-2 reserved ........................................ always reads 0 1 pci #2 (agp) arbiter disable 0 respond to greq# signal .....................default 1 do not respond to greq# signal 0 pci #1 arbiter disable 0 respond to all req# signals..................default 1 do not respond to any req# signals, including preq# this port can be enabled for read/write access by setting bit-7 of device 0 configuration register 78. configuration space i/o all registers in the VT82C691 (listed above) are addressed via the following configuration mechanism: mechanism #1 these ports respond only to double-word accesses. byte or word accesses will be passed on unchanged. port cfb-cf8 - configuration address ......................... rw 31 configuration space enable 0 disabled................................................. default 1 convert configuration data port writes to configuration cycles on the pci bus 30-24 reserved ........................................always reads 0 23-16 pci bus number used to choose a specific pci bus in the system 15-11 device number used to choose a specific device in the system (devices 0 and 1 are defined for the VT82C691) 10-8 function number used to choose a specific function if the selected device supports multiple functions (only function 0 is defined for the VT82C691). 7-2 register number (also called the "offset") used to select a specific dword in the VT82C691 configuration space 1-0 fixed ........................................always reads 0 port cff-cfc - configuration data .............................. rw refer to pci bus specification version 2.1 for further details on operation of the above configuration registers.
VT82C691 preliminary revision 1.0 july 16, 1998 - 21- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw register descriptions device 0 header registers - host bridge all registers are located in pci configuration space. they should be programmed using pci configuration mechanism 1 through cf8 / cfc with bus number, function number, and device number equal to zero . device 0 offset 1-0 - vendor id ........................................ ro 15-0 id code (reads 1106h to identify via technologies) device 0 offset 3-2 - device id .......................................... ro 15-0 id code (reads 0691h to identify the VT82C691) device 0 offset 5-4 - command ........................................ rw 15-10 reserved ........................................ always reads 0 9 fast back-to-back cycle enable ........................ ro 0 fast back-to-back transactions only allowed to the same agent ........................................default 1 fast back-to-back transactions allowed to different agents 8 serr# enable ...................................................... ro 0 serr# driver disabled ...........................default 1 serr# driver enabled (serr# is used to report parity errors if bit-6 is set). 7 address / data stepping ...................................... ro 0 device never does stepping....................default 1 device always does stepping 6 parity error response ........................................ rw 0 ignore parity errors & continue ..............default 1 take normal action on detected parity errors 5 vga palette snoop .............................................. ro 0 treat palette accesses normally ..............default 1 dont respond to palette accesses on pci bus 4 memory write and invalidate command .......... ro 0 bus masters must use mem write ..........default 1 bus masters may generate mem write & inval 3 special cycle monitoring .................................... ro 0 does not monitor special cycles .............default 1 monitors special cycles 2bus master .......................................................... ro 0 never behaves as a bus master 1 can behave as a bus master ....................default 1 memory space ...................................................... ro 0 does not respond to memory space 1 responds to memory space ....................default 0 i/o space .......................................................... ro 0 does not respond to i/o space ...............default 1 responds to i/o space device 0 offset 7-6 - status ........................................... rwc 15 detected parity error 0 no parity error detected ......................... default 1 error detected in either address or data phase. this bit is set even if error response is disabled (command register bit-6). ......write one to clear 14 signaled system error (serr# asserted) ........................................always reads 0 13 signaled master abort 0 no abort received .................................. default 1 transaction aborted by the master ................... ....................................write one to clear 12 received target abort 0 no abort received .................................. default 1 transaction aborted by the target...................... ....................................... write 1 to clear 11 signaled target abort ........................always reads 0 0 target abort never signaled 10-9 devsel# timing 00 fast 01 medium....................................always reads 01 10 slow 11 reserved 8 data parity error detected 0 no data parity error detected ................. default 1 error detected in data phase. set only if error response enabled via command bit-6 = 1 and VT82C691 was initiator of the operation in which the error occurred. .......write one to clear 7 fast back-to-back capable ...............always reads 1 6 reserved ........................................always reads 0 5 66mhz capable ..................................always reads 0 4 supports new capability list .............always reads 1 3-0 reserved ........................................always reads 0 device 0 offset 8 - revision id ......................................... ro 7-0 VT82C691 chip revision code device 0 offset 9 - programming interface ..................... ro 7-0 interface identifier ...........................always reads 00 device 0 offset a - sub class code .................................. ro 7-0 sub class code .......reads 00 to indicate host bridge device 0 offset b - base class code ................................. ro 7-0 base class code .. reads 06 to indicate bridge device device 0 offset d - latency timer .................................. rw specifies the latency timer value in pci bus clocks. 7-3 guaranteed time slice for cpu ................default=0 2-0 reserved (fixed granularity of 8 clks) .. always read 0 bits 2-1 are writeable but read 0 for pci specification compatibility. the programmed value may be read back in offset 75 bits 5-4 (pci arbitration 1).
VT82C691 preliminary revision 1.0 july 16, 1998 - 22- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 0 host bridge header registers (continued) device 0 offset e - header type ....................................... ro 7-0 header type code ............reads 00: single function device 0 offset f - built in self test (bist) .................... ro 7 bist supported ......reads 0: no supported functions 6-0 reserved ........................................ always reads 0 device 0 offset 13-10 - graphics aperture base ............ rw 31-28 upper programmable base address bits ....... def=0 27-20 lower programmable base address bits ...... def=0 these bits behave as if hardwired to 0 if the corresponding graphics aperture size register bit (device 1 offset 84h) is 0. 27 26 25 24 23 22 21 20 (this register) 76 5 4 3 2 1 0 (gr aper size) rw rw rw rw rw rw rw rw 1m rw rw rw rw rw rw rw 0 2m rw rw rw rw rw rw 0 0 4m rw rw rw rw rw 0 0 0 8m rwrwrwrw0000 16m rwrwrw00000 32m rwrw000000 64m rw0000000 128m 00000000 256m 19-0 reserved ................................ always reads 00008 note: the locations in the address range defined by this register are prefetchable. device 0 offset 2d-2c C subsystem vendor id .......... r/w1 15-0 subsystem vendor id ...............................default = 0 this register may be written once and is then read only. device 0 offset 2f-2e C subsystem id ......................... r/w1 15-0 subsystem id ............................................default = 0 this register may be written once and is then read only. device 0 offset 37-34 - capability pointer ...................... ro contains an offset from the start of configuration space. 31-0 agp capability list pointer ........ always reads a0h
VT82C691 preliminary revision 1.0 july 16, 1998 - 23- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 0 configuration registers - host bridge these registers are normally programmed once at system initialization time. host cpu control device 0 offset 50 C host cpu protocol control 1 ........ rw 7 cpu hardwired ioq (in order queue) size default per strap on pin mecc3 / cke3. during reset, ha7 is driven low if mecc3 is sampled low. this register can be written 0 to restrict the chip to one level of ioq. 0 1-level 1 4-level 6 read-around-write 0 disable ...................................................default 1enable 5 i/o write deferable 0 disable ...................................................default 1enable 4 defer retry when hlock active 0 disable ...................................................default 1enable 3 cpu read pci retry 0 disable ...................................................default 1enable 2 cpu read pci deferred 0 disable ...................................................default 1enable 1 cpu read dram timing 0 start dram access after snoop phase complete .....default 1 start dram access before snoop phase complete 0 pci master read dram timing 0 start dram access after snoop phase complete .....default 1 start dram access before snoop phase complete device 0 offset 51 C host cpu protocol control 2 ........ rw 7 cpu read dram 0ws for back-to-back read transactions 0 disable................................................... default 1enable setting this bit enables maximum read performance by allowing continuous 0 wait state reads for pipelined line reads. if this bit is not set, there will be at least 1t idle time between read transactions. 6 cpu write dram 0ws for back-to-back write transactions 0 disable................................................... default 1enable setting this bit enables maximum write performance by allowing continuous 0 wait state writes for pipelined line writes ands sustained 3t single writes. if this bit is not set, there will be at least 1t idle time between write transactions. 5 dram read request rate 0 3t .................................................... default 12t 4 reserved (do not program) ....................default = 0 3 reserved (do not program) ....................default = 0 2 cpu read dram prefetch buffer depth 0 1-level prefetch buffer ........................... default 1 4-level prefetch buffer 1 cpu-to-dram post-write buffer depth 0 1-level post-write buffer ........................ default 1 4-level post-write buffer 0 concurrent pci master / host operation 0 disable (cpu bus will be occupied (bpri asserted) during the entire pci operation period) ................................................... default 1 enable (cpu bus is only requested before ads# assertion) device 0 offset 52 C dynamic defer time ...................... rw 7 gtl i/o buffer pullup ....... default = mecc4 strap 0 disable 1enable the default value of this bit is determined by a strap on the mecc4 pin during reset. 6-5 reserved ........................................always reads 0 4-0 snoop stall count 00 disable dynamic defer ........................... default 1-1f snoop stall count
VT82C691 preliminary revision 1.0 july 16, 1998 - 24- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw dram control these registers are normally set at system initialization time and not accessed after that during normal system operation. some of these registers, however, may need to be programmed using specific sequences during power-up initialization to properly detect the type and size of installed memory (refer to the via technologies 82c691 bios porting guide for details). table 3. system memory map space start size address range comment dos 0 640k 00000000-0009ffff cacheable vga 640k 128k 000a0000-000bffff used for smm bios 768k 16k 000c0000-000c3fff shadow ctrl 1 bios 784k 16k 000c4000-000c7fff shadow ctrl 1 bios 800k 16k 000c8000-000cbfff shadow ctrl 1 bios 816k 16k 000cc000-000cffff shadow ctrl 1 bios 832k 16k 000d0000-000d3fff shadow ctrl 2 bios 848k 16k 000d4000-000d7fff shadow ctrl 2 bios 864k 16k 000d8000-000dbfff shadow ctrl 2 bios 880k 16k 000dc000-000dffff shadow ctrl 2 bios 896k 64k 000e0000-000effff shadow ctrl 3 bios 960k 64k 000f0000-000fffff shadow ctrl 3 sys 1mb 00100000-dram top can have hole bus d top dram top-fffeffff init 4g-64k 64k fffeffff-ffffffff 000f xxxx alias device 0 offset 59-58 - dram ma map type ............... rw 15-13 bank 5/4 ma map type (edo/fpg) 000 8-bit column address 001 9-bit column address 010 10-bit column address ..........................default 011 11-bit column address 100 12-bit column address (64mb) 101 reserved 11x reserved bank 5/4 ma map type (sdram) 0xx 16mbit sdram.....................................default 100 64mbit sdram (x4, x8, x16, 4-bank x32) 101 reserved 11x reserved 12 bank 5/4 virtual channel enable ............. default=0 11-9 bank 7/6 ma map type (see above) 8 bank 7/6 virtual channel enable ............. default=0 7-5 bank 1/0 ma map type (see above) 4 bank 1/0 virtual channel enable ............. default=0 3-1 bank 3/2 ma map type (see above) 0 bank 3/2 virtual channel enable ............. default=0 device 0 offset 5a-5f C dram row ending address: all of the registers in this group default to 01h: offset 5a C bank 0 ending (ha[30:23]) .................... rw offset 5b C bank 1 ending (ha[30:23]) .................... rw offset 5c C bank 2 ending (ha[30:23]) .................... rw offset 5d C bank 3 ending (ha[30:23]) .................... rw offset 5e C bank 4 ending (ha[30:23]) .................... rw offset 5f C bank 5 ending (ha[30:23]) .................... rw offset 56 C bank 6 ending (ha[30:23]) ..................... rw offset 57 C bank 7 ending (ha[30:23]) ..................... rw note : bios is required to fill the ending address registers for all banks even if no memory is populated. the endings have to be in incremental order. device 0 offset 60 C dram type ................................... rw 7-6 dram type for bank 7/6 00 fast page mode dram (fpg).............. default 01 edo dram (edo) 10 sdram double data rate (ddr sdram-ii) 11 sdram single data rate (sdr sdram) 5-4 dram type for bank 5/4 .....................default=fpg 3-2 dram type for bank 3/2 .....................default=fpg 1-0 dram type for bank 1/0 .....................default=fpg table 4. memory address mapping table edo/fp dram ma: 13 12 11 10 9 8 7 6 5 4 3 2 1 0 8-bit col (000) 23 22 21 11 20 19 10 18 9 17 8 16 7 15 6 14 5 13 4 12 3 row bits col bits 9-bit col (001) 24 23 22 21 20 11 19 10 18 9 17 8 16 7 15 6 14 5 13 4 12 3 row bits col bits 10-bit col (010) 25 24 23 21 22 20 11 19 10 18 9 17 8 16 7 15 6 14 5 13 4 12 3 row bits col bits 11-bit col (011) 26 25 23 24 21 22 20 11 19 10 18 9 17 8 16 7 15 6 14 5 13 4 12 3 row bits col bits 12-bit col (100) 27 25 26 23 24 21 22 20 11 19 10 18 9 17 8 16 7 15 6 14 5 13 4 12 3 row bits col bits sdram ma: 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16mb (0xx) 11 11 22 pc 21 24 20 23 19 10 18 9 17 8 16 7 15 6 14 5 13 4 12 3 row bits col bits 64mb (100) 2/4 bank x4, x8, x16; 4-bank x32 24 24 13 13 12 12 22 pc 21 26 20 25 19 10 18 9 17 8 16 7 15 6 14 5 11 4 23 3 x4: 10 col x8: 9 col x16: 8 col x32: 8 col "pc" = "precharge control" (refer to sdram specifications) 16mb 11x10, 11x9, and 11x8 configurations supported 64mb x4: 12x10 4bank, 13x10 2bank x8: 12x9 4bank, 13x9 2bank x16: 12x8 4bank, 13x8 2bank x32: 11x8 4bank
VT82C691 preliminary revision 1.0 july 16, 1998 - 25- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 0 offset 61 - shadow ram control 1 ................. rw 7-6 cc000h-cffffh 00 read/write disable ..................................default 01 write enable 10 read enable 11 read/write enable 5-4 c8000h-cbfffh 00 read/write disable ..................................default 01 write enable 10 read enable 11 read/write enable 3-2 c4000h-c7fffh 00 read/write disable ..................................default 01 write enable 10 read enable 11 read/write enable 1-0 c0000h-c3fffh 00 read/write disable ..................................default 01 write enable 10 read enable 11 read/write enable device 0 offset 62 - shadow ram control 2 ................. rw 7-6 dc000h-dffffh 00 read/write disable ..................................default 01 write enable 10 read enable 11 read/write enable 5-4 d8000h-dbfffh 00 read/write disable ..................................default 01 write enable 10 read enable 11 read/write enable 3-2 d4000h-d7fffh 00 read/write disable ..................................default 01 write enable 10 read enable 11 read/write enable 1-0 d0000h-d3fffh 00 read/write disable ..................................default 01 write enable 10 read enable 11 read/write enable device 0 offset 63 - shadow ram control 3 ................. rw 7-6 e0000h-effffh 00 read/write disable ................................. default 01 write enable 10 read enable 11 read/write enable 5-4 f0000h-fffffh 00 read/write disable ................................. default 01 write enable 10 read enable 11 read/write enable 3-2 memory hole 00 none .................................................... default 01 512k-640k 10 15m-16m (1m) 11 14m-16m (2m) 1-0 smi mapping control smm non-smm code data code data 00 dram dram pci pci 01 dram dram dram dram 10 invalid invalid dram pci 11 dram dram invalid invalid
VT82C691 preliminary revision 1.0 july 16, 1998 - 26- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 0 offset 64 - dram timing for banks 0,1 ......... rw device 0 offset 65 - dram timing for banks 2,3 ......... rw device 0 offset 66 - dram timing for banks 4,5 ......... rw device 0 offset 67 - dram timing for banks 6,7 ......... rw fpg / edo settings for registers 64-67 7 ras precharge time 03t 1 4t .....................................................default 6 ras pulse width 04t 1 5t .....................................................default 5-4 cas read pulse width 00 1t 01 2t 10 3t .....................................................default 11 4t note: edo will not automatically reduce the cas pulse width. for edo type drams, use 00 if cas width = 1 is to be used. 3 cas write pulse width 01t 1 2t .....................................................default 2 ma-to-cas delay 01t 1 2t .....................................................default 1 ras to ma delay 0 1t .....................................................default 12t 0 reserved ........................................ always reads 0 sdram settings for registers 64-67 7 precharge command to active command period 0t rp = 2t 1t rp = 3t ............................................... default 6 active command to precharge command period 0t ras = 5t 1t ras = 6t ............................................. default 5-4 cas latency sdram sdram-ii 00 1t n/a 01 2t n/a 10 3t 2t, 2.5t ............................... default 11 n/a 3t 3 ddr write enable (sdram-ii only) 0 disable 1 enable ................................................... default 2 active command to cmd command period 02t 1 3t .................................................... default 1-0 bank interleave 00 no interleave ......................................... default 01 2-way 10 4-way 11 reserved
VT82C691 preliminary revision 1.0 july 16, 1998 - 27- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 0 offset 68 - dram control ................................ rw 7 sdram open page control 0 always precharge sdram banks when accessing edo/fpg drams.................default 1 sdram banks remain active when accessing edo/fpg banks 6 bank page control 0 allow only pages of the same bank active... def 1 allow pages of different banks to be active 5 edo pipeline burst rate 0 x-2-2-2- 2 -2-2-2......................................default 1 x-2-2-2- 3 -2-2-2 4 reserved (do not program)........................ default = 0 3edo test mode 0 disable ...................................................default 1enable 2 burst refresh 0 disable ...................................................default 1 enable (burst 4 times) 1 reserved ........................................ always reads 0 0 system frequency divider .................................. ro 0 cpu/pci frequency ratio = 2x (66 mhz) 1 cpu/pci frequency ratio = 3x (100 mhz) this bit is latched from mecc0 at the rising edge of reset#. note: md0 is internally pulled up for edo detection. device 0 offset 69 C dram clock select ........................ rw 7 dram operating frequency ............................. ro 0 same as cpu frequency (66/100 mhz) 1 same as agp frequency (66 mhz) this bit is latched from mecc2 at the rising edge of reset#. 6-0 reserved ........................................ always reads 0 device 0 offset 6a - refresh counter ............................. rw 7-0 refresh counter (in units of 16 cpuclks) 00 dram refresh disabled....................... default 01 32 cpuclks 02 48 cpuclks 03 64 cpuclks 04 80 cpuclks 05 96 cpuclks the programmed value is the desired number of 16- cpuclk units minus one. device 0 offset 6b - dram arbitration control .......... rw 7-6 arbitration parking policy 00 park at last bus owner ............................ default 01 park at cpu side 10 park at agp side 11 reserved 5-4 reserved ........................................always reads 0 3-1 suspend refresh rate 000 refresh disable 001 15.6 usec 010 31.2 usec 011 64.4 usec 100 125 usec 101 256 usec 110 reserved 111 reserved 0 multi-page open 0 disable (page registers marked invalid and no page register update which causes non page- mode operation) 1 enable ................................................... default
VT82C691 preliminary revision 1.0 july 16, 1998 - 28- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 0 offset 6c - sdram control ............................. rw 7 reserved (do not program) ...................... must be 0 6 dram start cycle 0 concurrent with cache hit detection (for 66mhz operation) ...........................default 1 after cache hit detection (for 100mhz operation) 5 md-to-hd pop 0 normal ...................................................default 1 add 1t latency to improve md setup time at 100 mhz 4 ddr write-to-read turnaround 0 1t turnaround (i.e., 3t from write command to read command) .................................default 1 2t turnaround 3 single rw burst stop command 0 disable ...................................................default 1 enable bst command to sdram to allow fast single-cycle pipeline 2-0 sdram operation mode select 000 normal sdram mode ..........................default 001 nop command enable 010 all-banks-precharge command enable (cpu-to-dram cycles are converted to all-banks-precharge commands). 011 msr enable cpu-to-dram cycles are converted to commands and the commands are driven on ma[13:0]. the bios selects an appropriate host address for each row of memory such that the right commands are generated on ma[13:0]. 100 cbr cycle enable (if this code is selected, cas-before-ras refresh is used; if it is not selected, ras-only refresh is used) 101 reserved 11x reserved device 0 offset 6d - dram drive strength................... rw 7 mab output disable 0 banks 0-3 use maa; banks 4-7 use mab... def 1 disable mab (all memory banks use maa) 6-5 delay dram read latch 00 disable................................................... default 01 0.5 ns 10 1.0 ns 11 2.0 ns 4 md drive 0 8 ma .................................................... default 16 ma 3 sdram command drive (sras#, scas#, swe#) 0 16ma .................................................... default 1 24ma 2 ma[2:13] / we# drive 0 16ma .................................................... default 1 24ma 1 cas# drive 0 8 ma .................................................... default 1 12 ma 0 ras# drive 0 16ma .................................................... default 1 24ma
VT82C691 preliminary revision 1.0 july 16, 1998 - 29- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 0 offset 6e - ecc control ................................... rw 7 ecc / ecmode select 0 ecc checking and reporting ................default 1 ecc checking, reporting, and correcting 6 reserved ........................................ always reads 0 5 enable serr# on ecc / ec multi-bit error 0 dont assert serr# for multi-bit errors..... def 1 assert serr# for multi-bit errors 4 enable serr# on ecc / ec single-bit error 0 dont assert serr# for single-bit errors..... def 1 assert serr# for single-bit errors 3 reserved ........................................ always reads 0 2 ecc / ec enable - bank 5/4 (dimm 2) 0 disable (no ecc or ec for banks 5/4)...default 1 enable (ecc or ec per bit-7) 1 ecc / ec enable - bank 3/2 (dimm 1) 0 disable (no ecc or ec for banks 3/2)...default 1 enable (ecc or ec per bit-7) 0 ecc / ec enable - bank 1/0 (dimm 0) 0 disable (no ecc or ec for banks 1/0)...default 1 enable (ecc or ec per bit-7) error checking / correction may be enabled bank-pair by bank-pair (dimm by dimm) by using bits 0-2 above. bank pairs must be populated with 72-bit memory to enable for ec or ecc since the additional data bits must be present in either case. for this reason, if 64-bit memory is populated in a particular bank pair, the corresponding bit 0-2 should be set to 0 to disable both ec and ecc for that bank pair. for those bank pairs that have 72-bit memory available (and have the corresponding bit 0-2 set), either ec or ecc may be selected via bit-7 above (i.e., all enabled bank pairs will use ec or all will use ecc). if error checking / reporting only (ec) is selected, all read and write cycles will use normal timing. partial writes (with ec or ecc enabled) will use read-modify-write cycles to maintain correct error correction codes in the additional 8 data bits. if ec and ecc are disabled for a particular bank pair, partial writes to that bank pair will use the byte enables to write only the selected bytes (using normal write cycles and cycle timing). if error correction (ecc) is selected, the first read of a transaction will always have one additional cycle of latency. bit-7 bits 2-0 rmw error checking error correction 0/1 0 no no no 0 1 yes yes no 1 1 yes yes yes device 0 offset 6f - ecc status ................................... rwc 7 multi-bit error detected ............... write of 1 resets 6-4 multi-bit error dram bank ....................default=0 encoded value of the bank with the multi-bit error. 3 single-bit error detected .............. write of 1 resets 2-0 single-bit error dram bank ..................default=0 encoded value of the bank with the single-bit error.
VT82C691 preliminary revision 1.0 july 16, 1998 - 30- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw pci bus #1 control these registers are normally programmed once at system initialization time. device 0 offset 70 - pci buffer control ......................... rw 7 cpu to pci post-write 0 disable ...................................................default 1enable 6 pci master to dram post-write 0 disable ...................................................default 1enable 5 reserved (no function) ............................ default = 0 4 pci master to dram prefetch 0 disable ...................................................default 1enable 3 cpu-to-pci buffer available cycle reduction 0 normal operation ...................................default 1 reduce 1 cycle when the cpu-to-pci buffer becomes available after being full (pci and agp buses) 2 pci master read caching 0 disable ...................................................default 1enable 1 delay transaction 0 disable ...................................................default 1enable 0 slave device stopped idle cycle reduction 0 normal operation...................................default 1 reduce 1 pci idle cycle when stopped by a slave device (pci and agp buses) device 0 offset 71 - cpu to pci flow control 1 ........... rw 7 dynamic burst 0 disable................................................... default 1 enable (see note under bit-3 below) 6 byte merge 0 disable................................................... default 1enable 5 reserved (do not program) ........................default = 0 4 pci i/o cycle post write 0 disable................................................... default 1enable 3pci burst 0 disable................................................... default 1 enable (bit7=1 will override this option) bit-7 bit-3 operation 0 0 every write goes into the write buffer and no pci burst operations occur. 0 1 if the write transaction is a burst transaction, the information goes into the write buffer and burst transfers are later performed on the pci bus. if the transaction is not a burst, pci write occurs immediately (after a write buffer flush). 1 x every write transaction goes to the write buffer; burstable transactions will then burst on the pci bus and non-burstable wont. this is the normal setting. 2 pci fast back-to-back write 0 disable................................................... default 1enable 1 quick frame generation 0 disable................................................... default 1enable 0 1 wait state pci cycles 0 disable................................................... default 1enable
VT82C691 preliminary revision 1.0 july 16, 1998 - 31- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 0 offset 72 - cpu to pci flow control 2 ......... rwc 7 retry status 0 retry occurred less than retry limit ........default 1 retry occurred more than x times (where x is defined by bits 5-4) ................. write 1 to clear 6 retry timeout action 0 retry forever (record status only)..........default 1 flush buffer for write or return all 1s for read 5-4 retry limit 00 retry 2 times ..........................................default 01 retry 16 times 10 retry 4 times 11 retry 64 times 3 clear failed data and continue retry 0 flush the entire post-write buffer ...........default 1 when data is posting and master (or target) abort fails, pop the failed data if any, and keep posting 2 cpu backoff on pci read retry failure 0 disable ...................................................default 1 backoff cpu when reading data from pci and retry fails 1 reduce 1t for frame# generation 0 disable ...................................................default 1enable 0 reserved (do not program)........................ default = 0 device 0 offset 73 - pci master control 1 ..................... rw 7 reserved ........................................always reads 0 6 pci master 1-wait-state write 0 zero wait state trdy# response........... default 1 one wait state trdy# response 5 pci master 1-wait-state read 0 zero wait state trdy# response........... default 1 one wait state trdy# response 4 reserved (do not program) ....................default = 0 3 assert stop# after pci master write timeout 0 disable................................................... default 1enable 2 assert stop# after pci master read timeout 0 disable................................................... default 1enable 1 lock# function 0 disable................................................... default 1enable 0 pci master broken timer enable 0 disable................................................... default 1 enable. force into arbitration when there is no frame# 16 pciclks after the grant. device 0 offset 74 - pci master control 2 ..................... rw 7 pci master read prefetch by enhance command 0 always prefetch..................................... default 1 prefetch only if enhance command 6 pci master write merge 0 disable................................................... default 1enable 5-0 reserved ........................................always reads 0
VT82C691 preliminary revision 1.0 july 16, 1998 - 32- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 0 offset 75 - pci arbitration 1 ............................ rw 7 arbitration mechanism 0 pci has priority ......................................default 1 fair arbitration between pci and cpu 6 arbitration mode 0 req-based (arbitrate at end of req#)...default 1 frame-based (arbitrate at frame# assertion) 5-4 latency timer ........... read only, reads rx0d bits 2:1 3-0 pci master bus time-out (force into arbitration after a period of time) 0000 disable ...................................................default 0001 1x32 pciclks 0010 2x32 pciclks 0011 3x32 pciclks 0100 4x32 pciclks ... ... 1111 15x32 pciclks device 0 offset 76 - pci arbitration 2 ............................ rw 7 pci #2 master access pci #1 retry disconnect 0 disable (pci #2 will not be disconnected until access finishes).......................................default 1 enable (pci #2 will be disconnected if max retries are attempted without success) 6 cpu latency timer bit-0 .................................... ro 0 cpu has at least 1 pclk time slot when cpu has pci bus 1 cpu has no time slot 5-4 master priority rotation control 00 disabled (arbitration per rx75 bit-7) .....default 01 grant to cpu after every pci master grant 10 grant to cpu after every 2 pci master grants 11 grant to cpu after every 3 pci master grants with setting 01, the cpu will always be granted access after the current bus master completes, no matter how many pci masters are requesting. with setting 10, if other pci masters are requesting during the current pci master grant, the highest priority master will get the bus after the current master completes, but the cpu will be guaranteed to get the bus after that master completes. with setting 11, if other pci masters are requesting, the highest priority will get the bus next, then the next highest priority will get the bus, then the cpu will get the bus. in other words, with the above settings, even if multiple pci masters are continuously requesting the bus, the cpu is guaranteed to get access after every master grant (01), after every other master grant (10) or after every third master grant (11). 3-0 reserved ........................................ always reads 0 device 0 offset 77 - chip test mode ............................... rw 7-6 reserved (no function) ....................... always reads 0 5-0 reserved (do not use) ................................. default=0 device 0 offset 78 - pmu control ................................... rw 7 i/o port 22 access 0 cpu access to i/o address 22h is passed on to the pci bus ............................................ default 1 cpu access to i/o address 22h is processed internally 6 suspend refresh type 0 cbr refresh.......................................... default 1 self refresh 5 normal refresh 0 normal refresh using hclk.................. default 1 suspend refresh using susclk 4 dynamic clock control 0 normal (clock is always running) .......... default 1 clock to various internal functional blocks is disabled when those blocks are not being used 3 gckrun# de-assertion 0 gckrun# always low.......................... default 1 gckrun# could be high due to pckrun# 2 reserved ........................................always reads 0 1 pckrun# / gckrun# pin control 0 disable (pins are gpar & gserr#) ... default 1 enable (pins are gckrun# and pckrun#) 0 memory clock enable (cke) function 0 cke disable (pins used for mecc)...... default 1 cke enable (pins used for cke# signals) device 0 offset 7e C dll test mode .............................. rw 7-6 reserved (status) ..................................................ro 5-0 reserved (do not use) .................................default=0 device 0 offset 7f C dll test mode .............................. rw 7-0 reserved (do not use) .................................default=0
VT82C691 preliminary revision 1.0 july 16, 1998 - 33- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw gart / graphics aperture control the function of the graphics address relocation table (gart) is to translate virtual 32-bit addresses issued by an agp device into 4k-page based physical addresses for system memory access. in this translation, the upper 20 bits (a31- a12) are remapped, while the lower 12 address bits (a11-a0) are used unchanged. a one-level fully associative lookup scheme is used to implement the address translation. in this scheme, the upper 20 bits of the virtual address are used to point to an entry in a page table located in system memory. each page table entry contains the upper 20 bits of a physical address (a "physical page" address). for simplicity, each page table entry is 4 bytes. the total size of the page table depends on the gart range (called the "aperture size") which is programmable in the VT82C691. this scheme is shown in the figure below. 31 12 11 0 virtual page address page offset index tlb base page table 31 12 11 0 physical page address page offset figure 5. graphics aperture address translation since address translation using the above scheme requires an access to system memory, an on-chip cache (called a "translation lookaside buffer" or tlb) is utilized to enhance performance. the tlb in the 82c691 contains 16 entries. address "misses" in the tlb require an access of system memory to retrieve translation data. entries in the tlb are replaced using an lru (least recently used) algorithm. addresses are translated only for accesses within the "graphics aperture" (ga). the graphics aperture can be any power of two in size from 1mb to 256mb (i.e., 1mb, 2mb, 4mb, 8mb, etc). the base of the graphics aperture can be anywhere in the system virtual address space on an address boundary determined by the aperture size (e.g., if the aperture size is 4mb, the base must be on a 4mb address boundary). the graphics aperture base is defined in register offset 10 of device 0. the graphics aperture size and tlb table base are defined in the following register group (offsets 84 and 88 respectively) along with various control bits.
VT82C691 preliminary revision 1.0 july 16, 1998 - 34- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 0 offset 83-80 - gart/tlb control ................... rw 31-16 reserved ........................................ always reads 0 15-8 reserved (test mode status) ................................. ro 7 flush page tlb 0 disable ...................................................default 1enable 6-4 reserved (always program to 0) ........................ rw 3 pci#1 master address translation for ga access 0 addresses generated by pci #1 master accesses of the graphics aperture will not be translated ................................................default 1 pci #1 master ga addresses will be translated 2 pci#2 master address translation for ga access 0 addresses generated by pci #2 master accesses of the graphics aperture will not be translated ................................................default 1 pci #2 master ga addresses will be translated 1 cpu address translation for ga access 0 addresses generated by cpu accesses of the graphics aperture will not be translated ..... def 1 cpu ga addresses will be translated 0 agp address translation for ga access 0 addresses generated by agp accesses of the graphics aperture will not be translated ..... def 1 agp ga addresses will be translated note: for any master access to the graphics aperture range, snoop will not be performed. device 0 offset 84 - graphics aperture size .................. rw 7-0 graphics aperture size 11111111 1m 11111110 2m 11111100 4m 11111000 8m 11110000 16m 11100000 32m 11000000 64m 10000000 128m 00000000 256m 3-0 reserved ........................................always reads 0 offset 8b-88 - ga translation table base ..................... rw 31-12 graphics aperture translation table base. pointer to the base of the translation table in system memory used to map addresses in the aperture range (the pointer to the base of the "directory" table). 11-3 reserved ........................................always reads 0 2 pci master directly accesses dram if in gart range 0 disable................................................... default 1enable 1 graphics aperture enable 0 disable................................................... default 1enable note: to disable the graphics aperture, set this bit to 0 and set all bits of the graphics aperture size to 0. to enable the graphics aperture, set this bit to 1 and program the graphics aperture size to the desired aperture size. 0 translation table noncachable 0 cachable ................................................ default 1 non-cachable note: setting this bit will make the address range programmed in bits 31-12 of this register non- cachable to l1/l2 with the following bits masked per the graphics aperture size (offset 84 described above): address bit 17 masked if size bit-7 = 0 address bit 16 masked if size bit-6 = 0 address bit 15 masked if size bit-5 = 0 address bit 14 masked if size bit-4 = 0 address bit 13 masked if size bit-3 = 0 address bit 12 masked if size bit-2 = 0 address bit 11 masked if size bit-1 = 0 address bit 10 masked if size bit-0 = 0 note: if tlb miss, the tlb table is fetched by the address: gr ap trans table base [31:12] + a[27:22], a[21:12], 2b00
VT82C691 preliminary revision 1.0 july 16, 1998 - 35- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw agp control device 0 offset a3-a0 - agp capability identifier ........ ro 31-24 reserved ...................................... always reads 00 23-20 major specification revision ..... always reads 0001 major revision # of agp spec device conforms to 19-16 minor specification revision ..... always reads 0000 minor revision # of agp spec device conforms to 15-8 pointer to next item ........ always reads 00 (last item) 7-0 agp id .. (always reads 02 to indicate it is agp) device 0 offset a7-a4 - agp status ................................. ro 31-24 maximum agp requests ................ always reads 07 max # of agp requests the device can manage (8) 23-10 reserved .......................................always reads 0s 9 supports sideband addressing ........ always reads 1 8-2 reserved .......................................always reads 0s 1 2x rate supported value returned can be programmed by writing to rxac[3] 0 1x rate supported ............................. always reads 1 device 0 offset ab-a8 - agp command ....................... rw 31-24 request depth (reserved for target) .. always reads 0s 23-10 reserved ...................................... always reads 0s 9 sideband addressing enable 0 disable................................................... default 1enable 8agp enable 0 disable................................................... default 1enable 7-2 reserved ...................................... always reads 0s 12x mode enable 0 disable................................................... default 1enable 01x mode enable 0 disable................................................... default 1enable
VT82C691 preliminary revision 1.0 july 16, 1998 - 36- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 0 offset ac - agp control .................................. rw 7-4 reserved .......................................always reads 0s 3 2x rate supported (read also at rxa4[1]) 0 not supported .........................................default 1 supported 2 lpr in-order access ( force fence) 0 fence/flush functions not guaranteed. agp read requests (low/normal priority and high priority) may be executed before previously issued write requests...............................default 1 force all requests to be executed in order (automatically enables fence/flush functions). low (i.e., normal) priority agp read requests will never be executed before previously issued writes. high priority agp read requests may still be executed prior to previously issued write requests as required. 1 agp arbitration parking 0 disable ...................................................default 1 enable (ggnt# remains asserted until either greq# de-asserts or data phase ready) 0 arbitration priority between cpu-to-pci post write and pci master request after pci master access 0 cpu-to-pci write buffer has priority .....default 1 pci master has priority device 0 offset f0-f7 C bios scratch registers ........... rw 7-0 no hardware function ..............................default = 0 device 0 offset fd-fc C reserved .................................. rw 15-1 reserved ...................................... always reads 0s 0 reserved (do not program) ....................default = 0 device 0 offset ff-fe C reserved .................................. rw 15-0 reserved ............................................default = 00
VT82C691 preliminary revision 1.0 july 16, 1998 - 37- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 1 header registers - pci-to-pci bridge all registers are located in pci configuration space. they should be programmed using pci configuration mechanism 1 through cf8 / cfc with bus number of 0 and function number equal to 0 and device number equal to one . device 1 offset 1-0 - vendor id ........................................ ro 15-0 id code (reads 1106h to identify via technologies) device 1 offset 3-2 - device id .......................................... ro 15-0 id code (reads 8691h to identify the VT82C691 pci-to-pci bridge device) device 1 offset 5-4 - command ........................................ rw 15-10 reserved ........................................ always reads 0 9 fast back-to-back cycle enable ........................ ro 0 fast back-to-back transactions only allowed to the same agent ........................................default 1 fast back-to-back transactions allowed to different agents 8 serr# enable ...................................................... ro 0 serr# driver disabled ...........................default 1 serr# driver enabled (serr# is used to report parity errors if bit-6 is set). 7 address / data stepping ...................................... ro 0 device never does stepping....................default 1 device always does stepping 6 parity error response ........................................ rw 0 ignore parity errors & continue ..............default 1 take normal action on detected parity errors 5 vga palette snoop .............................................. ro 0 treat palette accesses normally ..............default 1 dont respond to palette writes on pci bus (10-bit decode of i/o addresses 3c6-3c9 hex) 4 memory write and invalidate command .......... ro 0 bus masters must use mem write ..........default 1 bus masters may generate mem write & inval 3 special cycle monitoring .................................... ro 0 does not monitor special cycles .............default 1 monitors special cycles 2bus master ......................................................... rw 0 never behaves as a bus master 1 enable to operate as a bus master on the primary interface on behalf of a master on the secondary interface ................................default 1 memory space ..................................................... rw 0 does not respond to memory space 1 enable memory space access .................default 0 i/o space ......................................................... rw 0 does not respond to i/o space 1 enable i/o space access ........................default device 1 offset 7-6 - status (primary bus) .................. rwc 15 detected parity error ........................always reads 0 14 signaled system error (serr#) .......always reads 0 13 signaled master abort 0 no abort received .................................. default 1 transaction aborted by the master with master-abort (except special cycles) .............. ....................................... write 1 to clear 12 received target abort 0 no abort received .................................. default 1 transaction aborted by the target with target- abort ....................................... write 1 to clear 11 signaled target abort ........................always reads 0 10-9 devsel# timing 00 fast 01 medium....................................always reads 01 10 slow 11 reserved 8 data parity error detected ...............always reads 0 7 fast back-to-back capable ...............always reads 0 6 user definable features .....................always reads 0 5 66mhz capable ..................................always reads 1 4 supports new capability list .............always reads 0 3-0 reserved ........................................always reads 0 device 1 offset 8 - revision id ......................................... ro 7-0 VT82C691 chip revision code (00=first silicon) device 1 offset 9 - programming interface ..................... ro this register is defined in different ways for each base/sub- class code value and is undefined for this type of device. 7-0 interface identifier ...........................always reads 00 device 1 offset a - sub class code .................................. ro 7-0 sub class code .reads 04 to indicate pci-pci bridge device 1 offset b - base class code ................................. ro 7-0 base class code .. reads 06 to indicate bridge device device 1 offset d - latency timer ................................... ro 7-0 reserved ........................................always reads 0 device 1 offset e - header type ...................................... ro 7-0 header type code .......... reads 01: pci-pci bridge device 1 offset f - built in self test (bist) ................... ro 7 bist supported ...... reads 0: no supported functions 6start test .......... write 1 to start but writes ignored 5-4 reserved ........................................always reads 0 3-0 response code ..........0 = test completed successfully
VT82C691 preliminary revision 1.0 july 16, 1998 - 38- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 1 offset 18 - primary bus number ...................... rw 7-0 primary bus number ............................... default = 0 this register is read write, but internally the chip always uses bus 0 as the primary. device 1 offset 19 - secondary bus number .................. rw 7-0 secondary bus number ........................... default = 0 note: pci#2 must use these bits to convert type 1 to type 0. device 1 offset 1a - subordinate bus number .............. rw 7-0 primary bus number ............................... default = 0 note: pci#2 must use these bits to decide if type 1 to type 1 command passing is allowed. device 1 offset 1c - i/o base ........................................... rw 7-4 i/o base ad[15:12] .......................... default = 1111b 3-0 i/o addressing capability ....................... default = 0 device 1 offset 1d - i/o limit .......................................... rw 7-4 i/o limit ad[15:12] ................................ default = 0 3-0 i/o addressing capability ....................... default = 0 device 1 offset 1f-1e - secondary status ....................... ro 15-0 reserved ..................................always reads 0000 device 1 offset 21-20 - memory base ............................. rw 15-4 memory base ad[31:20] ................ default = 0fffh 3-0 reserved ........................................always reads 0 device 1 offset 23-22 - memory limit (inclusive) ......... rw 15-4 memory limit ad[31:20] ........................default = 0 3-0 reserved ........................................always reads 0 device 1 offset 25-24 - prefetchable memory base ....... rw 15-4 prefetchable memory base ad[31:20] def = 0fffh 3-0 reserved ........................................always reads 0 device 1 offset 27-26 - prefetchable memory limit ..... rw 15-4 prefetchable memory limit ad[31:20] ................... ..............................................default = 0 3-0 reserved ........................................always reads 0
VT82C691 preliminary revision 1.0 july 16, 1998 - 39- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 1 offset 3f-3e C pci-to-pci bridge control ..... rw 15-4 reserved ........................................ always reads 0 3 vga-present on agp 0 forward vga accesses to pci bus #1...default 1 forward vga accesses to pci bus #2 / agp note: vga addresses are memory a0000-bffffh and i/o addresses 3b0-3bbh, 3c0-3cfh and 3d0- 3dfh (10-bit decode). "mono" text mode uses b0000-b7fffh and "color" text mode uses b8000- bffffh. graphics modes use axxxxh. mono vga uses i/o addresses 3bx-3cxh and color vga uses 3cx-3dxh. if an mda is present, a vga will not use the 3bxh i/o addresses and b0000-b7fffh memory space; if not, the vga will use those addresses to emulate mda modes. 2 block / forward isa i/o addresses 0 forward all i/o accesses to the agp bus if they are in the range defined by the i/o base and i/o limit registers (device 1 offset 1c-1d) .....................................................default 1 do not forward i/o accesses to the agp bus that are in the 100-3ffh address range even if they are in the range defined by the i/o base and i/o limit registers. 1-0 reserved ........................................ always reads 0
VT82C691 preliminary revision 1.0 july 16, 1998 - 40- register descriptions 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw device 1 configuration registers - pci-to-pci bridge pci bus #2 control device 1 offset 40 - cpu-to-pci #2 flow control 1 .. rw 7 cpu-pci #2 post write 0 disable ...................................................default 1enable 6 cpu-pci #2 dynamic burst 0 disable ...................................................default 1enable 5 cpu-pci #2 one wait state burst write 0 disable ...................................................default 1enable 4 pci #2 to dram prefetch 0 disable ...................................................default 1enable 3 pci master allowed before cpu-to-pci post write buffer is not flushed 0 disable ...................................................default 1enable this option is always enabled for pci #1 2 mda present on pci #2 0 forward mda accesses to agp.............default 1 forward mda accesses to pci #1 note: forward despite io / memory base / limit note: mda (monochrome display adapter) addresses are memory addresses b0000h-b7fffh and i/o addresses 3b4-3b5h, 3b8-3bah, and 3bfh (10-bit decode). 3bc-3be are reserved for printers. note: if rx3e bit-3 is 0, this bit is a don't care (mda accesses are forwarded to the pci bus). 1 pci #2 master read caching 0 disable ...................................................default 1enable 0 pci #2 delay transaction 0 disable ...................................................default 1enable table 5. vga/mda memory/io redirection 3e[3] vga pres. 40[2] mda pres. vga is on mda is on axxxx, b8xxx access b0000 -b7fff access 3cx, 3dx i/o 3bx i/o 0 - pci pci pci pci pci pci 1 0 agp agp agp agp agp agp 1 1 agp pci agp pci agp pci device 1 offset 41 - cpu-to-pci #2 flow control 2 .. rwc 7 retry status 0 no retry occurred................................... default 1 retry occurred ........................ write 1 to clear 6 retry timeout action 0 no action taken except to record status ....... def 1 flush buffer for write or return all 1s for read 5-4 retry count 00 retry 2, backoff cpu ............................ default 01 retry 4, backoff cpu 10 retry 16, backoff cpu 11 retry 64, backoff cpu 3 post write data on abort 0 flush entire post-write buffer on target-abort or master abort ....................................... default 1 pop one data output on target-abort or master- abort 2 cpu backoff on pci #2 read retry timeout 0 disable................................................... default 1enable 1 cpu to pci #2 i/o write posting 0 disable................................................... default 1enable 0 reserved ........................................always reads 0 device 1 offset 42 - pci #2 master control ................... rw 7 read prefetch for enhance command 0 always perform prefetch ....................... default 1 prefetch only if enhance command 6 pci #2 master one wait state write 0 disable................................................... default 1enable 5 pci #2 master one wait state read 0 disable................................................... default 1enable 4 extend pci #2 internal master for efficient handling of dummy request cycles 0 disable................................................... default 1enable this bit is normally set to 1. 3 reserved ........................................always reads 0 2 fast response / read caching prefetch disable 0 normal operation................................... default 1 disable prefetch when doing fast response to the previous delay transaction or doing read caching 1-0 reserved ........................................always reads 0
VT82C691 preliminary revision 1.0 july 16, 1998 - 41- electrical specifications 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw e lectrical s pecifications absolute maximum ratings parameter min max unit ambient operating temperature 0 70 o c storage temperature -55 125 o c input voltage -0.5 5.5 volts output voltage (v cc = 3.1 - 3.6v) -0.5 v cc + 0.5 volts note: stress above the conditions listed may cause permanent damage to the device. functional operation of this device should be restricted to the conditions described under operating conditions. dc characteristics ta-0-70 o c, v cc =5v+/-5%, gnd=0v symbol parameter min max unit condition v il input low voltage -0.50 0.8 v v ih input high voltage 2.0 v cc +0.5 v v ol output low voltage - 0.45 v i ol =4.0ma v oh output high voltage 2.4 - v i oh =-1.0ma i il input leakage current - +/-10 ua 0 VT82C691 preliminary revision 1.0 july 16, 1998 - 42- electrical specifications 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw table 7. ac characteristics - cpu cycle timing parameter min max unit notes ns 0pf ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
VT82C691 preliminary revision 1.0 july 16, 1998 - 43- electrical specifications 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw table 8. ac characteristics - dram interface timing parameter min max unit notes ras[5:0]# valid delay from hclk rising (edo) ns 0pf cs[5:0]# valid delay from hclk rising (sdram) ns cas[7:0]# valid delay from hclk rising (edo) ns dqm[7:0]# valid delay from hclk rising (sdram) ns sras[a,b,c]# valid delay from hclk rising (sdram) ns scas[a,b,c]# valid delay from hclk rising (sdram) ns swe[a,b,c]# valid delay from hclk rising (sdram) ns ma[11:2] valid delay from hclk rising on first clock after ras# asserts ns ma[1:0] valid delay from hclk rising (burst) ns ma[11:0] flow through delay from ha for first read cycle ns swe[a,b,c]# valid delay from hclk rising (edo) ns table 9. ac characteristics - data timing parameter min max unit notes hd valid delay from hclk rising ns 0pf hd setup time to hclk rising ns hd hold time from hclk rising ns md valid delay from hclk rising ns md setup time to hclk rising (sdram) ns md setup time to hclk falling (edo) ns md hold time from hclk rising (sdram) ns md hold time from hclk falling (edo) ns
VT82C691 preliminary revision 1.0 july 16, 1998 - 44- electrical specifications 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw table 10. ac characteristics - pci cycle timing parameter min max unit notes ad[31:0] valid delay from pclk rising (address phase) 5.0 11 ns 50pf ad[31:0] valid delay from pclk rising (data phase) 5.0 11 ns ad[31:0] setup time to hclk rising 1.5 ns ad[31:0] hold time to hclk rising 0.8 ns cbe[3:0]# setup time to hclk rising 1.0 ns frame# setup time to hclk rising 5.8 ns trdy# setup time to hclk rising 5.5 ns irdy# setup time to hclk rising 5.0 ns stop# setup time to hclk rising 3.8 ns devsel# setup time to hclk rising 4.8 ns req[3:0]# setup time to hclk rising 8.7 ns cbe[3:0]# hold time to hclk rising 0.2 ns frame# hold time to hclk rising 0.3 ns trdy# hold time to hclk rising 0.4 ns irdy# hold time to hclk rising 0.3 ns stop# hold time to hclk rising 0.8 ns devsel# hold time to hclk rising 0.3 ns req[3:0]# hold time to hclk rising 0.8 ns cbe[3:0]# valid delay from pclk rising 2.9 7.5 ns frame# valid delay from pclk rising 2.8 7.3 ns trdy# valid delay from pclk rising 5.8 15.0 ns irdy# valid delay from pclk rising 2.9 7.5 ns stop# valid delay from pclk rising 2.9 7.5 ns devsel# valid delay from pclk rising 2.8 7.3 ns gnt[3:0]#, valid delay from pclk rising 2.3 6.0 ns cbe[3:0]# ,float delay from hclk rising 3.4 8.7 ns frame# ,float delay from hclk rising 3.4 9.8 ns trdy# ,float delay from hclk rising 3.8 10.0 ns irdy# ,float delay from hclk rising 3.9 10.0 ns stop# ,float delay from hclk rising 3.4 9.8 ns devsel# ,float delay from hclk rising 3.8 9.9 ns
VT82C691 preliminary revision 1.0 july 16, 1998 - 45- electrical specifications 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw table 11. ac characteristics C pci-66 cycle timing parameter min max unit notes ad[31:0] valid delay from hclk rising (address phase) 3.1 5.4 ns 0pf ad[31:0] valid delay from hclk rising (data phase) 3.1 5.4 ns ad[31:0] setup time to hclk rising 1.4 ns ad[31:0] hold time to hclk rising 0.3 ns cbe[3:0]# setup time to hclk rising 0.9 ns frame# setup time to hclk rising 4.0 ns trdy# setup time to hclk rising 2.0 ns irdy# setup time to hclk rising 4.5 ns stop# setup time to hclk rising 2.7 ns devsel# setup time to hclk rising 4.4 ns cbe[3:0]# hold time to hclk rising 0.4 ns frame# hold time to hclk rising 0.6 ns trdy# hold time to hclk rising 0.4 ns irdy# hold time to hclk rising 0.2 ns stop# hold time to hclk rising 0.7 ns devsel# hold time to hclk rising 0.4 ns cbe[3:0]# valid delay from hclk rising 2.1 5.3 ns frame# valid delay from hclk rising 2.1 5.2 ns trdy# valid delay from hclk rising 2.1 5.3 ns irdy# valid delay from hclk rising 2.1 5.4 ns stop# valid delay from hclk rising 2.1 5.2 ns devsel# valid delay from hclk rising 2.1 5.6 ns gnt#, valid delay from hclk rising 2.5 5.2 ns cbe[3:0]# ,float delay from hclk rising 3.3 11 ns frame# ,float delay from hclk rising 1.7 7 ns trdy# ,float delay from hclk rising 1.7 7 ns irdy# ,float delay from hclk rising 3.3 11 ns stop# ,float delay from hclk rising 1.7 7 ns devsel# ,float delay from hclk rising 2.1 8 ns
VT82C691 preliminary revision 1.0 july 16, 1998 - 46- electrical specifications 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw table 12. ac characteristics - agp (1x) cycle timing parameter min max unit notes gd[31:0] valid delay from hclk rising (request phase) 1.1 5.2 ns 0 pf gd[31:0] valid delay from hclk rising (data phase) 0.2 ns gd[31:0] valid delay from hclk rising (data phase) 2.0 5.0 ns gd[31:0] hold time to hclk rising 0.6 ns gbe[3:0]#, setup time to hclk rising 5.0 ns gpipe#, setup time to hclk rising 3.6 ns sba[7:0], setup time to hclk rising 4.7 ns girdy#, setup time to hclk rising 4.7 ns grbf#, setup time to hclk rising 4.7 ns gbe[3:0]#, hold time from hclk rising 0.8 ns gpipe, hold time from hclk rising 0.3 ns sba[7:0], hold time from hclk rising 0.2 ns girdy#, hold time from hclk rising 0.3 ns grbf#, hold time from hclk rising 0.1 ns st[2:0], valid delay from hclk rising 2.4 5.5 ns gtrdy#, valid delay from hclk rising 2.6 5.7 ns greq# setup time to hclk rising 3.5 ns greq# hold time to hclk rising 0.3 ns ggnt# valid delay from hclk rising 1.5 5.5 ns table 13. ac characteristics - agp (2x) cycle timing parameter min max unit notes gd[31:0] setup time to gds[1:0]# 0.4 ns 0 pf gbe[3:0]# setup time to gds[1:0]# 0.4 ns sba[7:0] setup time to sbs# 0.7 ns gds[1:0]# to hclk rising (t2) setup time 0.7 ns sbs# to hclk rising setup time 0.7 ns gd[31:0] hold time from to gds[1:0]# falling 0.7 ns gbe[3:0]# hold time from to gds[1:0]# falling 0.7 ns sba[7:0] hold time from to sbs# falling 0.4 ns gds[1:0]# to hclk rising (t2) hold time 1.5 ns sbs# to hclk rising hold time 1.5 ns gd[31:0] valid delay before gds[1:0]# 1.8 3.7 ns gd[31:0] valid delay after gds[1:0]# 1.8 3.8 ns gd[31:0] float to active delay 2.0 5.2 ns gd[31:0] active to float delay 1.7 4.4 ns gds[1:0]# falling delay from hclk rising 3.4 8.9 ns gds[1:0]# rising delay from hclk rising 6.0 15.6 ns
VT82C691 preliminary revision 1.0 july 16, 1998 - 47- mechanical specifications 7hfkqrorjlhv ,qf : h& : h&r rq qq qhfw hfw m echanical s pecifications figure 8. mechanical specifications - 492-pin ball grid array package 492-pin bga $ % & ' ( ) * + - . / 0 1 3 5 7 8 9 : < $$ $% $& $' $( $) ? ? % $ ; 5() 5() & 6($7,1* 3/$1( ? 7<3 & ? ? ? ?; ? ? & &$ % 66 6 6 5() ? ; $ % & ' ( ) * + - . / 0 1 3 5 7 8 9 : < $$ $% $& $' $( $) 3,1 &251(5 ? ; 5() 5() 35x35x2.33 mm jedec spec mo-151 97& <<::55 7$,:$1 ///////// &0 y = date code year w = date code week r = chip revision l = lot code

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